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author | Richard Henderson <rth@redhat.com> | 2016-03-25 16:37:13 -0700 |
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committer | Jeff Law <law@gcc.gnu.org> | 2016-03-25 17:37:13 -0600 |
commit | 5fca7b666313db331730a5c90e3c64b0e1402af9 (patch) | |
tree | 14ef8e8afe597205dcd22402e659b00e620572b0 | |
parent | d7796e23a4a973afdc45897de4932c1e1bd3e898 (diff) | |
download | gcc-5fca7b666313db331730a5c90e3c64b0e1402af9.zip gcc-5fca7b666313db331730a5c90e3c64b0e1402af9.tar.gz gcc-5fca7b666313db331730a5c90e3c64b0e1402af9.tar.bz2 |
re PR target/70120 ([aarch64] -g causes Assembler messages: Error: unaligned opcodes detected in executable segment)
2016-03-25 Richard Henderson <rth@redhat.com>
PR target/70120
* config/aarch64/aarch64.c (aarch64_asm_output_pool_epilogue): New.
* config/aarch64/aarch64-protos.h: Declare it.
* config/aarch64/aarch64.h (ASM_OUTPUT_POOL_EPILOGUE): New.
PR target/70120
* gcc.target/aarch64/pr70120-1.c: New.
* gcc.target/aarch64/pr70120-2.c: New.
* gcc.target/aarch64/pr70120-3.c: New.
From-SVN: r234486
-rw-r--r-- | gcc/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-protos.h | 4 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64.c | 12 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64.h | 2 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr70120-1.c | 19 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr70120-2.c | 17 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr70120-3.c | 22 |
8 files changed, 90 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6c9e945..af2bda6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-03-25 Richard Henderson <rth@redhat.com> + + PR target/70120 + * config/aarch64/aarch64.c (aarch64_asm_output_pool_epilogue): New. + * config/aarch64/aarch64-protos.h: Declare it. + * config/aarch64/aarch64.h (ASM_OUTPUT_POOL_EPILOGUE): New. + 2016-03-25 Alan Modra <amodra@gmail.com> PR target/70052 diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index dced209..58c9d0d 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -429,4 +429,8 @@ bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset); bool aarch64_operands_ok_for_ldpstp (rtx *, bool, enum machine_mode); bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, enum machine_mode); extern bool aarch64_nopcrelative_literal_loads; + +extern void aarch64_asm_output_pool_epilogue (FILE *, const char *, + tree, HOST_WIDE_INT); + #endif /* GCC_AARCH64_PROTOS_H */ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ed0daa5..b7086dd 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5555,6 +5555,18 @@ aarch64_select_rtx_section (machine_mode mode, return default_elf_select_rtx_section (mode, x, align); } +/* Implement ASM_OUTPUT_POOL_EPILOGUE. */ +void +aarch64_asm_output_pool_epilogue (FILE *f, const char *, tree, + HOST_WIDE_INT offset) +{ + /* When using per-function literal pools, we must ensure that any code + section is aligned to the minimal instruction length, lest we get + errors from the assembler re "unaligned instructions". */ + if ((offset & 3) && aarch64_can_use_per_function_literal_pools_p ()) + ASM_OUTPUT_ALIGN (f, 2); +} + /* Costs. */ /* Helper function for rtx cost calculation. Strip a shift expression diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index ec96ce3..7750d1c 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -928,4 +928,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define EXTRA_SPECS \ { "asm_cpu_spec", ASM_CPU_SPEC } +#define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue + #endif /* GCC_AARCH64_H */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5552489..a5f548f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2016-03-25 Richard Henderson <rth@redhat.com> + + PR target/70120 + * gcc.target/aarch64/pr70120-1.c: New. + * gcc.target/aarch64/pr70120-2.c: New. + * gcc.target/aarch64/pr70120-3.c: New. + 2016-03-25 Patrick Palka <ppalka@gcc.gnu.org> PR c++/62212 diff --git a/gcc/testsuite/gcc.target/aarch64/pr70120-1.c b/gcc/testsuite/gcc.target/aarch64/pr70120-1.c new file mode 100644 index 0000000..31a5e94 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr70120-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-Og -fschedule-insns -mno-pc-relative-literal-loads -g" } */ + +typedef short v32u16 __attribute__ ((vector_size (32))); +typedef int v32u32 __attribute__ ((vector_size (32))); +typedef long v32u64 __attribute__ ((vector_size (32))); +typedef __int128 u128; +typedef __int128 v32u128 __attribute__ ((vector_size (32))); + +int +foo(int u16_0, int u32_0, int u64_0, u128 u128_0, int u16_1, int u32_1, int u64_1, u128 u128_1, v32u16 v32u16_0, v32u32 v32u32_0, v32u64 v32u64_0, v32u128 v32u128_0, v32u16 v32u16_1, v32u32 v32u32_1, v32u64 v32u64_1, v32u128 v32u128_1) +{ + v32u32_1 ^= (v32u32) ~ v32u64_0; + v32u32_1 %= (v32u32) - v32u16_1 | 1; + v32u16_1 -= (v32u16) v32u16_1; + v32u64_0 *= (v32u64){~ u128_0, v32u16_1[5], v32u16_0[15], v32u32_1[4]}; + v32u16_0 /= (v32u16){0x574c, ~u128_1, v32u128_1[0], u64_1, v32u64_0[1], v32u64_1[2], 0, 0x8ce6, u128_1, 0x5e69} |1; + return v32u16_0[0] + v32u16_0[6] + v32u16_0[8] + v32u16_0[9] + v32u32_0[0] + v32u32_0[1] + v32u32_0[2] + v32u32_0[3] + v32u32_0[4] + v32u32_0[6] + v32u64_0[0] + v32u64_0[2] + v32u64_0[3] + v32u128_0[0] + v32u128_0[1] + v32u32_1[0] + v32u32_1[2] + v32u64_1[2] + v32u64_1[3] + v32u128_1[1]; +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr70120-2.c b/gcc/testsuite/gcc.target/aarch64/pr70120-2.c new file mode 100644 index 0000000..0110224 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr70120-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-Og -freorder-functions -g3 -mcmodel=large" } */ + +typedef short v32u16 __attribute__ ((vector_size (32))); +typedef int v32u32 __attribute__ ((vector_size (32))); +typedef long v32u64 __attribute__ ((vector_size (32))); +typedef __int128 u128; +typedef __int128 v32u128 __attribute__ ((vector_size (32))); + +int +foo (int u16_0, int u32_0, int u64_0, u128 u128_0, int u16_1, int u32_1, v32u16 v32u16_0, v32u32 v32u32_0, v32u64 v32u64_0, v32u128 v32u128_0, v32u16 v32u16_1, v32u32 v32u32_1, v32u64 v32u64_1, v32u128 v32u128_1) +{ + u128_0 <<= 0x6c; + v32u16_1 %= (v32u16) { 1, 64, 0xf294, 0, u32_1, v32u32_1[6], ~u128_0, 0x2912, v32u32_0[2]} | 1; + v32u16_0 ^= (v32u16){-v32u16_1[11], -u32_1, 64, ~u128_0, 0, 1, 64, ~u64_0, 0}; + return u16_0 + u32_0 + u16_1 + v32u16_0[0] + v32u32_0[1] + v32u32_0[2] + v32u32_0[4] + v32u32_0[6] + v32u64_0[0] + v32u64_0[1] + v32u64_0[2] + v32u64_0[3] + v32u128_0[0] + v32u128_0[1] + v32u16_1[0] + v32u32_1[7] + v32u64_1[0] + v32u64_1[1] + v32u64_1[2] + v32u64_1[3] + v32u128_1[0] + v32u128_1[1]; +} diff --git a/gcc/testsuite/gcc.target/aarch64/pr70120-3.c b/gcc/testsuite/gcc.target/aarch64/pr70120-3.c new file mode 100644 index 0000000..2b70df7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr70120-3.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -ffunction-sections -mno-pc-relative-literal-loads -g3" } */ + +typedef unsigned short u16; +typedef unsigned short v32u16 __attribute__((vector_size(32))); +typedef unsigned int u32; +typedef unsigned int v32u32 __attribute__((vector_size(32))); +typedef unsigned long long u64; +typedef unsigned long long v32u64 __attribute__((vector_size(32))); +typedef unsigned __int128 u128; +typedef unsigned __int128 v32u128 __attribute__((vector_size(32))); +u128 __attribute__((noinline, noclone)) +foo(u16 u16_0, u32 u32_0, u64 u64_0, u128 u128_0, u16 u16_1, u32 u32_1, u64 u64_1, u128 u128_1, v32u16 v32u16_0, v32u32 v32u32_0, v32u64 v32u64_0, v32u128 v32u128_0, v32u16 v32u16_1, v32u32 v32u32_1, v32u64 v32u64_1, v32u128 v32u128_1) +{ + v32u128_1 %= (v32u128)v32u32_1 | 1; + u16_1 /= ((u32)~(u128)(((u128)0xa1 << 0))) | 1; + v32u32_0 += (v32u32){(u16)v32u16_1[9], (u16)v32u16_1[14], (u32)-v32u32_0[7], ((u64)(u32)(((u128)0x43bc59e9 << 0))), ((u32)(u32)(((u128)0x14a47ba8f240a6 << 0))), (u128)v32u128_1[1], (u16)u16_1, (u64)-u64_1}; + return u16_0 + u32_0 + u64_0 + u128_0 + u16_1 + u32_1 + u64_1 + u128_1 + v32u16_0[0] + v32u16_0[1] + v32u16_0[2] + v32u16_0[3] + v32u16_0[4] + v32u16_0[5] + v32u16_0[6] + v32u16_0[7] + v32u16_0[8] + v32u16_0[9] + v32u16_0[10] + v32u16_0[11] + v32u16_0[12] + v32u16_0[13] + v32u16_0[14] + v32u16_0[15] + v32u32_0[0] + v32u32_0[1] + v32u32_0[2] + v32u32_0[3] + v32u32_0[4] + v32u32_0[5] + v32u32_0[6] + v32u32_0[7] + v32u64_0[0] + v32u64_0[1] + v32u64_0[2] + v32u64_0[3] + v32u128_0[0] + v32u128_0[1] + v32u16_1[0] + v32u16_1[1] + v32u16_1[2] + v32u16_1[3] + v32u16_1[4] + v32u16_1[5] + v32u16_1[6] + v32u16_1[7] + v32u16_1[8] + v32u16_1[9] + v32u16_1[10] + v32u16_1[11] + v32u16_1[12] + v32u16_1[13] + v32u16_1[14] + v32u16_1[15] + v32u32_1[0] + v32u32_1[1] + v32u32_1[2] + v32u32_1[3] + v32u32_1[4] + v32u32_1[5] + v32u32_1[6] + v32u32_1[7] + v32u64_1[0] + v32u64_1[1] + v32u64_1[2] + v32u64_1[3] + v32u128_1[0] + v32u128_1[1]; +} +int main() +{ +} |