Fix big-endian code generation

From-SVN: r50952

3 files changed, 31 insertions, 15 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7c17ca1..db0b67e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2002-03-18  Bernd Schmidt  <bernds@redhat.com>
+
+	* config/arm/arm.c (arm_gen_movstrqi): Use gen_lowpart instead
+	of gen_rtx_SUBREG.
+	(arm_reload_out_hi): Use gen_lowpart instead of
+	gen_rtx_SUBREG to access QImode components.
+	* config/arm/arm.md: Disable zero_extend split for QImode
+	subregs in BIG_ENDIAN mode.
+	(storehi_bigend): Match use of least significant byte.
+	(storeinthi): Remove extraneous SUBREG.
+	Add missing sonstruction of operands[2].
+	(movhi): Use gen_lowpart in place of gen_rtx_SUBREG.
+	(movqi): Use gen_lowpart in place of gen_rtx_SUBREG.
+	Replace gen_rtx (SUBREG) with gen_rtx_SUBREG.
+
 2002-03-18  Aldy Hernandez  <aldyh@redhat.com>
 
         * config/rs6000/rs6000.h (PREDICATE_CODES): Add PARALLEL to
@@ -4459,7 +4474,7 @@ Mon Feb	 4 19:23:19 2002  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
 	* config/arm/arm.c (arm_hard_regno_mode_ok): Allow any value in
 	any geenral register.
 
-2001-02-04  Bernd Schmidt  <bernds@redhat.com>
+2001-02-04  Bernd Schmidt  <bernds@redhat.com>s
 
 	* cfgrtl.c (force_nonfallthru_and_redirect): Don't try to redirect
 	the entry block.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 921411a..4b17758 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -4544,8 +4544,8 @@ arm_gen_movstrqi (operands)
 	  RTX_UNCHANGING_P (mem) = dst_unchanging_p;
 	  MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
 	  MEM_SCALAR_P (mem) = dst_scalar_p;
-	  emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
-	  
+	  emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
+
 	  if (--last_bytes)
 	    {
 	      tmp = gen_reg_rtx (SImode);
@@ -4563,7 +4563,7 @@ arm_gen_movstrqi (operands)
 	  RTX_UNCHANGING_P (mem) = dst_unchanging_p;
 	  MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
 	  MEM_SCALAR_P (mem) = dst_scalar_p;
-	  emit_move_insn (mem, gen_rtx_SUBREG (HImode, part_bytes_reg, 0));
+	  emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
 	  last_bytes -= 2;
 	  if (last_bytes)
 	    {
@@ -4581,7 +4581,7 @@ arm_gen_movstrqi (operands)
 	  RTX_UNCHANGING_P (mem) = dst_unchanging_p;
 	  MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
 	  MEM_SCALAR_P (mem) = dst_scalar_p;
-	  emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));	  
+	  emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
 	}
     }
 
@@ -5119,23 +5119,23 @@ arm_reload_out_hi (operands)
     {
       emit_insn (gen_movqi (gen_rtx_MEM (QImode, 
 					 plus_constant (base, offset + 1)),
-			    gen_rtx_SUBREG (QImode, outval, 0)));
+			    gen_lowpart (QImode, outval)));
       emit_insn (gen_lshrsi3 (scratch,
 			      gen_rtx_SUBREG (SImode, outval, 0),
 			      GEN_INT (8)));
       emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
-			    gen_rtx_SUBREG (QImode, scratch, 0)));
+			    gen_lowpart (QImode, scratch)));
     }
   else
     {
       emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
-			    gen_rtx_SUBREG (QImode, outval, 0)));
+			    gen_lowpart (QImode, outval)));
       emit_insn (gen_lshrsi3 (scratch,
 			      gen_rtx_SUBREG (SImode, outval, 0),
 			      GEN_INT (8)));
       emit_insn (gen_movqi (gen_rtx_MEM (QImode,
 					 plus_constant (base, offset + 1)),
-			    gen_rtx_SUBREG (QImode, scratch, 0)));
+			    gen_lowpart (QImode, scratch)));
     }
 }
 
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 1db601a..af0c9ec 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3386,7 +3386,7 @@
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0)))
    (clobber (match_operand:SI 2 "s_register_operand" ""))]
-  "TARGET_ARM && (GET_CODE (operands[1]) != MEM)"
+  "TARGET_ARM && (GET_CODE (operands[1]) != MEM) && ! BYTES_BIG_ENDIAN"
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
   ""
@@ -4285,7 +4285,7 @@
   [(set (match_dup 4) (match_dup 3))
    (set (match_dup 2)
 	(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
-   (set (match_operand 1 "" "")	(subreg:QI (match_dup 2) 0))]
+   (set (match_operand 1 "" "")	(subreg:QI (match_dup 2) 3))]
   "TARGET_ARM"
   "
   {
@@ -4309,7 +4309,7 @@
 (define_expand "storeinthi"
   [(set (match_operand 0 "" "")
 	(subreg:QI (match_operand 1 "" "") 0))
-   (set (match_dup 3) (subreg:QI (match_dup 2) 0))]
+   (set (match_dup 3) (match_dup 2))]
   "TARGET_ARM"
   "
   {
@@ -4348,6 +4348,7 @@
 
     operands[3] = adjust_address (op0, QImode, 1);
     operands[0] = adjust_address (operands[0], QImode, 0);
+    operands[2] = gen_lowpart (QImode, operands[2]);
   }"
 )
 
@@ -4410,7 +4411,7 @@
 	        }
 
 	      emit_insn (gen_movsi (reg, GEN_INT (val)));
-	      operands[1] = gen_rtx_SUBREG (HImode, reg, 0);
+	      operands[1] = gen_lowpart (HImode, reg);
 	    }
           else if (!arm_arch4)
 	    {
@@ -4807,7 +4808,7 @@
 	      rtx reg = gen_reg_rtx (SImode);
 
 	      emit_insn (gen_movsi (reg, operands[1]));
-	      operands[1] = gen_rtx_SUBREG (QImode, reg, 0);
+	      operands[1] = gen_lowpart (QImode, reg);
 	    }
          if (GET_CODE (operands[0]) == MEM)
 	   operands[1] = force_reg (QImode, operands[1]);
@@ -4850,7 +4851,7 @@
           if (GET_CODE (operands[0]) != REG)
 	    abort ();
 
-          operands[0] = gen_rtx (SUBREG, SImode, operands[0], 0);
+          operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
           emit_insn (gen_movsi (operands[0], operands[1]));
           DONE;
        }