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authorSegher Boessenkool <segher@kernel.crashing.org>2017-05-19 13:29:21 +0200
committerSegher Boessenkool <segher@gcc.gnu.org>2017-05-19 13:29:21 +0200
commit5d3ae76af134ab1f901f05223e57fc4ef951b18c (patch)
tree58d1e883a54e2e25917097c06c8dd3dc265e9d50
parent3a6461f307f6204f2b415a3fc94fa21dc7cbe3ec (diff)
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rs6000: Make constant formation a tiny bit better
If we cannot load a constant into a register in one insn, and that constant is a valid mask (for rotate instructions), we currently prefer to load -1 and then mask it. This patch makes us not do that if instead we could use two add or or instructions, since those are sometimes faster on certain CPUs (and never are slower). * config/rs6000/rs6000.md (splitter to load of -1 and mask): Don't use this splitter if two add or or instructions would also work for the constant we want to generate. From-SVN: r248265
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/config/rs6000/rs6000.md1
2 files changed, 7 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9e386f7..9006383 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2017-05-19 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/rs6000.md (splitter to load of -1 and mask): Don't
+ use this splitter if two add or or instructions would also work for
+ the constant we want to generate.
+
2017-05-19 Richard Biener <rguenther@suse.de>
PR build/80821
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 26baaaf..799d786 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8732,6 +8732,7 @@
(match_operand:DI 1 "const_int_operand"))]
"TARGET_POWERPC64
&& num_insns_constant (operands[1], DImode) > 1
+ && !IN_RANGE (INTVAL (operands[1]), -0x80000000, 0xffffffff)
&& rs6000_is_valid_and_mask (operands[1], DImode)"
[(set (match_dup 0)
(const_int -1))