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| author | Andrew Stubbs <ams@codesourcery.com> | 2020-03-03 17:36:49 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2020-03-18 12:53:26 +0000 |
| commit | 5a80a6c3e5f800de63a2eadd8ae3e6822172a718 (patch) | |
| tree | 5ee88f8662b75daa8225d12132d1c506109f0ef2 | |
| parent | 11cf25c40e3f586d19474108c78a2dfad7925902 (diff) | |
| download | gcc-5a80a6c3e5f800de63a2eadd8ae3e6822172a718.zip gcc-5a80a6c3e5f800de63a2eadd8ae3e6822172a718.tar.gz gcc-5a80a6c3e5f800de63a2eadd8ae3e6822172a718.tar.bz2 | |
amdgcn: Add cond_add/sub/and/ior/xor for all vector modes
2020-03-18 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (COND_MODE): Delete.
(COND_INT_MODE): Delete.
(cond_op): Add "mult".
(cond_<expander><mode>): Use VEC_ALLREG_MODE.
(cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/gcn/gcn-valu.md | 27 |
2 files changed, 20 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 114d299..dac1d41 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-03-18 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (COND_MODE): Delete. + (COND_INT_MODE): Delete. + (cond_op): Add "mult". + (cond_<expander><mode>): Use VEC_ALLREG_MODE. + (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE. + 2020-03-18 Richard Biener <rguenther@suse.de> PR middle-end/94206 diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index a8034f7..68d89fa 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2903,19 +2903,15 @@ DONE; }) -; FIXME this should be VEC_REG_MODE, but not all dependencies are implemented. -(define_mode_iterator COND_MODE [V64SI V64DI V64SF V64DF]) -(define_mode_iterator COND_INT_MODE [V64SI V64DI]) - -(define_code_iterator cond_op [plus minus]) +(define_code_iterator cond_op [plus minus mult]) (define_expand "cond_<expander><mode>" - [(match_operand:COND_MODE 0 "register_operand") + [(match_operand:VEC_ALLREG_MODE 0 "register_operand") (match_operand:DI 1 "register_operand") - (cond_op:COND_MODE - (match_operand:COND_MODE 2 "gcn_alu_operand") - (match_operand:COND_MODE 3 "gcn_alu_operand")) - (match_operand:COND_MODE 4 "register_operand")] + (cond_op:VEC_ALLREG_MODE + (match_operand:VEC_ALLREG_MODE 2 "gcn_alu_operand") + (match_operand:VEC_ALLREG_MODE 3 "gcn_alu_operand")) + (match_operand:VEC_ALLREG_MODE 4 "register_operand")] "" { operands[1] = force_reg (DImode, operands[1]); @@ -2927,15 +2923,16 @@ DONE; }) +;; TODO smin umin smax umax (define_code_iterator cond_bitop [and ior xor]) (define_expand "cond_<expander><mode>" - [(match_operand:COND_INT_MODE 0 "register_operand") + [(match_operand:VEC_ALLREG_INT_MODE 0 "register_operand") (match_operand:DI 1 "register_operand") - (cond_bitop:COND_INT_MODE - (match_operand:COND_INT_MODE 2 "gcn_alu_operand") - (match_operand:COND_INT_MODE 3 "gcn_alu_operand")) - (match_operand:COND_INT_MODE 4 "register_operand")] + (cond_bitop:VEC_ALLREG_INT_MODE + (match_operand:VEC_ALLREG_INT_MODE 2 "gcn_alu_operand") + (match_operand:VEC_ALLREG_INT_MODE 3 "gcn_alu_operand")) + (match_operand:VEC_ALLREG_INT_MODE 4 "register_operand")] "" { operands[1] = force_reg (DImode, operands[1]); |