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author | David S. Miller <davem@davemloft.net> | 2011-10-23 21:50:56 +0000 |
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committer | David S. Miller <davem@gcc.gnu.org> | 2011-10-23 14:50:56 -0700 |
commit | 5a53588ff09224348d467976fb196225ecf9c8d9 (patch) | |
tree | ec7972f920b9997fc298d272d22bae34b1efa531 | |
parent | 0bcf216b2a353f0ec40c4def6a24b00f9586a922 (diff) | |
download | gcc-5a53588ff09224348d467976fb196225ecf9c8d9.zip gcc-5a53588ff09224348d467976fb196225ecf9c8d9.tar.gz gcc-5a53588ff09224348d467976fb196225ecf9c8d9.tar.bz2 |
Use a macro instead of a constant to test for sparc integer regnos.
* config/sparc/sparc.h (SPARC_FIRST_INT_REG, SPARC_LAST_INT_REG,
SPARC_INT_REG_P): Define.
(HARD_REGNO_NREGS): Use SPARC_INT_REG_P.
(REGNO_OK_FOR_INDEX_P): Likewise.
* config/sparc/sparc.c (gen_df_reg): Likewise.
(eligible_for_return_delay): Likewise.
(eligible_for_sibcall_delay): Likewise.
(sparc_legitimate_address_p): Likewise.
(emit_save_or_restore_regs): Likewise.
(registers_ok_for_ldd_peep): Likewise.
* config/spac/sparc.md (DI mode splitters): Likewise.
(SF mode const splitters): Likewise.
(DF mode splitters): Likewise.
(32-bit DI mode logical op splitters): Likewise.
From-SVN: r180350
-rw-r--r-- | gcc/ChangeLog | 17 | ||||
-rw-r--r-- | gcc/config/sparc/sparc.c | 18 | ||||
-rw-r--r-- | gcc/config/sparc/sparc.h | 12 | ||||
-rw-r--r-- | gcc/config/sparc/sparc.md | 40 |
4 files changed, 55 insertions, 32 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 42766f1..e647a60 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2011-10-23 David S. Miller <davem@davemloft.net> + + * config/sparc/sparc.h (SPARC_FIRST_INT_REG, SPARC_LAST_INT_REG, + SPARC_INT_REG_P): Define. + (HARD_REGNO_NREGS): Use SPARC_INT_REG_P. + (REGNO_OK_FOR_INDEX_P): Likewise. + * config/sparc/sparc.c (gen_df_reg): Likewise. + (eligible_for_return_delay): Likewise. + (eligible_for_sibcall_delay): Likewise. + (sparc_legitimate_address_p): Likewise. + (emit_save_or_restore_regs): Likewise. + (registers_ok_for_ldd_peep): Likewise. + * config/spac/sparc.md (DI mode splitters): Likewise. + (SF mode const splitters): Likewise. + (DF mode splitters): Likewise. + (32-bit DI mode logical op splitters): Likewise. + 2011-10-23 Paolo Carlini <paolo.carlini@oracle.com> PR c++/50841 diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index ba88315..415ece8 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -2640,7 +2640,7 @@ gen_df_reg (rtx reg, int low) int regno = REGNO (reg); if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) - regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; + regno += (TARGET_ARCH64 && SPARC_INT_REG_P (regno)) ? 1 : 2; return gen_rtx_REG (DFmode, regno); } @@ -3124,7 +3124,7 @@ eligible_for_return_delay (rtx trial) /* If this instruction sets up floating point register and we have a return instruction, it can probably go in. But restore will not work with FP_REGS. */ - if (regno >= 32) + if (! SPARC_INT_REG_P (regno)) return (TARGET_V9 && !epilogue_renumber (&pat, 1) && get_attr_in_uncond_branch_delay (trial) @@ -3166,7 +3166,7 @@ eligible_for_sibcall_delay (rtx trial) a `restore' insn can go into the delay slot. */ if (GET_CODE (SET_DEST (pat)) != REG || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24) - || REGNO (SET_DEST (pat)) >= 32) + || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat)))) return 0; /* If it mentions %o7, it can't go in, because sibcall will clobber it @@ -3486,11 +3486,11 @@ sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict) } else { - if ((REGNO (rs1) >= 32 + if ((! SPARC_INT_REG_P (REGNO (rs1)) && REGNO (rs1) != FRAME_POINTER_REGNUM && REGNO (rs1) < FIRST_PSEUDO_REGISTER) || (rs2 - && (REGNO (rs2) >= 32 + && (! SPARC_INT_REG_P (REGNO (rs2)) && REGNO (rs2) != FRAME_POINTER_REGNUM && REGNO (rs2) < FIRST_PSEUDO_REGISTER))) return 0; @@ -4729,17 +4729,17 @@ emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base, if (reg0 && reg1) { - mode = i < 32 ? DImode : DFmode; + mode = SPARC_INT_REG_P (i) ? DImode : DFmode; regno = i; } else if (reg0) { - mode = i < 32 ? SImode : SFmode; + mode = SPARC_INT_REG_P (i) ? SImode : SFmode; regno = i; } else if (reg1) { - mode = i < 32 ? SImode : SFmode; + mode = SPARC_INT_REG_P (i) ? SImode : SFmode; regno = i + 1; offset += 4; } @@ -7794,7 +7794,7 @@ registers_ok_for_ldd_peep (rtx reg1, rtx reg2) return 0; /* Integer ldd is deprecated in SPARC V9 */ - if (TARGET_V9 && REGNO (reg1) < 32) + if (TARGET_V9 && SPARC_INT_REG_P (REGNO (reg1))) return 0; return (REGNO (reg1) == REGNO (reg2) - 1); diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index d9ce9df..76240f0 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -597,6 +597,8 @@ extern enum cmodel sparc_cmodel; #define FIRST_PSEUDO_REGISTER 103 +#define SPARC_FIRST_INT_REG 0 +#define SPARC_LAST_INT_REG 31 #define SPARC_FIRST_FP_REG 32 /* Additional V9 fp regs. */ #define SPARC_FIRST_V9_FP_REG 64 @@ -614,6 +616,10 @@ extern enum cmodel sparc_cmodel; #define SPARC_FP_REG_P(REGNO) \ ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) +/* Nonzero if REGNO is an int reg. */ +#define SPARC_INT_REG_P(REGNO) \ +(((unsigned) (REGNO)) <= SPARC_LAST_INT_REG) + /* Argument passing regs. */ #define SPARC_OUTGOING_INT_ARG_FIRST 8 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) @@ -703,7 +709,7 @@ extern enum cmodel sparc_cmodel; #define HARD_REGNO_NREGS(REGNO, MODE) \ ((REGNO) == SPARC_GSR_REG ? 1 : \ (TARGET_ARCH64 \ - ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \ + ? (SPARC_INT_REG_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM \ ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ : (GET_MODE_SIZE (MODE) + 3) / 4) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) @@ -1382,8 +1388,8 @@ do { \ has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(REGNO) \ -((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \ - || (REGNO) == FRAME_POINTER_REGNUM \ +(SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \ + || (REGNO) == FRAME_POINTER_REGNUM \ || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index f53bddd..c6454f5 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1794,10 +1794,10 @@ && (! TARGET_V9 || (! TARGET_ARCH64 && ((GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) < 32))))" + && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))))" [(clobber (const_int 0))] { emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), @@ -1827,10 +1827,10 @@ && (! TARGET_V9 || (! TARGET_ARCH64 && ((GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) < 32))))" + && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))))" [(clobber (const_int 0))] { rtx set_dest = operands[0]; @@ -2050,7 +2050,7 @@ (define_split [(set (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "fp_const_high_losum_operand" ""))] - "REG_P (operands[0]) && REGNO (operands[0]) < 32" + "REG_P (operands[0]) && SPARC_INT_REG_P (REGNO (operands[0]))" [(set (match_dup 0) (high:SF (match_dup 1))) (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))]) @@ -2184,7 +2184,7 @@ (match_operand:DF 1 "const_double_operand" ""))] "TARGET_FPU && (GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) && ! const_zero_operand (operands[1], GET_MODE (operands[0])) && reload_completed" [(clobber (const_int 0))] @@ -2240,10 +2240,10 @@ "(! TARGET_V9 || (! TARGET_ARCH64 && ((GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) < 32)))) + && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0]))))))) && reload_completed" [(clobber (const_int 0))] { @@ -2346,10 +2346,10 @@ "reload_completed && ! TARGET_ARCH64 && ((GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) < 32))" + && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" [(clobber (const_int 0))] { rtx set_dest = operands[0]; @@ -4654,10 +4654,10 @@ "#" "&& reload_completed && ((GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) < 32))" + && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5))) (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))] "operands[3] = gen_highpart (SImode, operands[0]); @@ -4731,10 +4731,10 @@ "#" "&& reload_completed && ((GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) < 32))" + && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5))) (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))] "operands[3] = gen_highpart (SImode, operands[0]); @@ -4821,10 +4821,10 @@ "! TARGET_ARCH64 && reload_completed && ((GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) < 32))" + && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)])) (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))] { @@ -4856,10 +4856,10 @@ "#" "&& reload_completed && ((GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) < 32))" + && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5)))) (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))] "operands[3] = gen_highpart (SImode, operands[0]); @@ -5133,10 +5133,10 @@ "#" "&& reload_completed && ((GET_CODE (operands[0]) == REG - && REGNO (operands[0]) < 32) + && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG - && REGNO (SUBREG_REG (operands[0])) < 32))" + && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0)))) (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))] "operands[2] = gen_highpart (SImode, operands[0]); |