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authorKito Cheng <kito.cheng@sifive.com>2024-01-19 10:30:16 +0800
committerKito Cheng <kito.cheng@sifive.com>2024-01-19 10:40:53 +0800
commit565935f93a7da629da89b05812a3e8c43287598f (patch)
treec4b2cc292b8b87dfe9a4249ef4483a9cbc549efd
parent173852ab68a461bbee07f6420a927c16d9019081 (diff)
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RISC-V: Tweak the wording for the sorry message
Use "does not" rather than "cannot", because it's implementation issue. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_override_options_internal): Tweak sorry message.
-rw-r--r--gcc/config/riscv/riscv.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f1d5129..dd6e68a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options *opts)
We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */
if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
- sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
+ sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
"'V' Extension");
/* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
big-endian after finishing full coverage testing. */
if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
- sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
+ sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
/* Convert -march to a chunks count. */
riscv_vector_chunks = riscv_convert_vector_bits (opts);