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| author | Kewen Lin <linkw@linux.ibm.com> | 2022-05-11 01:18:30 -0500 |
|---|---|---|
| committer | Kewen Lin <linkw@linux.ibm.com> | 2022-05-11 02:21:37 -0500 |
| commit | 55aa130ef112c6f2c8ef85c218455464c6b29d60 (patch) | |
| tree | f8e849483ee1e31e046e2327f451765562164d4d | |
| parent | 9e1e962eac8d2a28fcd648a0f5c8eb0022abd8e4 (diff) | |
| download | gcc-55aa130ef112c6f2c8ef85c218455464c6b29d60.zip gcc-55aa130ef112c6f2c8ef85c218455464c6b29d60.tar.gz gcc-55aa130ef112c6f2c8ef85c218455464c6b29d60.tar.bz2 | |
rs6000: Fix constraint v with rs6000_constraints[RS6000_CONSTRAINT_v]
Currently we hardcode ALTIVEC_REGS for register constraint v and
RS6000_CONSTRAINT_v looks confusing, this is to fix it with
rs6000_constraints[RS6000_CONSTRAINT_v] to align with some other
existing register constraints with RS6000_CONSTRAINT_*.
gcc/ChangeLog:
* config/rs6000/constraints.md (register constraint v): Use
rs6000_constraints[RS6000_CONSTRAINT_v] instead of ALTIVEC_REGS.
| -rw-r--r-- | gcc/config/rs6000/constraints.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 7aaffd9..b361893 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -37,7 +37,7 @@ historically @code{f} was for single-precision and @code{d} was for double-precision floating point.") -(define_register_constraint "v" "ALTIVEC_REGS" +(define_register_constraint "v" "rs6000_constraints[RS6000_CONSTRAINT_v]" "An Altivec vector register (VR), @code{v0}@dots{}@code{v31}.") (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" |