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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-05-25 14:19:29 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-05-25 14:19:29 +0800 |
| commit | 53bd7622de70a4ca4a25cac953da3be2a24bc3c8 (patch) | |
| tree | e4e8bed494c6d798998b2799bdb97e90d404810f | |
| parent | c9a19621a07e246385ae075b61283140b23c3b5a (diff) | |
| download | gcc-53bd7622de70a4ca4a25cac953da3be2a24bc3c8.zip gcc-53bd7622de70a4ca4a25cac953da3be2a24bc3c8.tar.gz gcc-53bd7622de70a4ca4a25cac953da3be2a24bc3c8.tar.bz2 | |
RISC-V: Remove FRM_REGNUM dependency for rtx conversions
According to RVV ISA:
The conversions use the dynamic rounding mode in frm, except for the rtz
variants, which round towards zero.
So rtz conversion patterns should not have FRM dependency.
We can't support mode switching for FRM yet since rvv intrinsic doc is
not updated but
I think this patch is correct.
gcc/ChangeLog:
* config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz
instructions.
Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
| -rw-r--r-- | gcc/config/riscv/vector.md | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 9afef0d..15f66ef 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7072,10 +7072,8 @@ (match_operand 5 "const_int_operand" " i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:<VCONVERT> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))] @@ -7142,10 +7140,8 @@ (match_operand 5 "const_int_operand" " i, i") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:VWCONVERTI (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")) (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] @@ -7233,10 +7229,8 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:<VNCONVERT> (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] |