diff options
| author | zhengnannan <zhengnannan@huawei.com> | 2020-10-20 17:53:04 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2020-10-20 17:53:04 +0100 |
| commit | 4fb0ee84ad8c9b789e2465c85ea048e3320365b0 (patch) | |
| tree | 39c24190972d8d74b54d8ce5d3d30ec238bb44aa | |
| parent | 16e4f1ad44e3c00b8b73c9e4ade3d236ea7044a8 (diff) | |
| download | gcc-4fb0ee84ad8c9b789e2465c85ea048e3320365b0.zip gcc-4fb0ee84ad8c9b789e2465c85ea048e3320365b0.tar.gz gcc-4fb0ee84ad8c9b789e2465c85ea048e3320365b0.tar.bz2 | |
AArch64: Add FLAG for get/set reg intrinsics [PR94442]
2020-10-20 Zhiheng Xie <xiezhiheng@huawei.com>
Nannan Zheng <zhengnannan@huawei.com>
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def: Add proper FLAG
for get/set reg intrinsics.
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd-builtins.def | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 4c23328..5bc596d 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -70,26 +70,26 @@ BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0, ALL) /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */ - BUILTIN_VDC (GETREG, get_dregoi, 0, ALL) - BUILTIN_VDC (GETREG, get_dregci, 0, ALL) - BUILTIN_VDC (GETREG, get_dregxi, 0, ALL) - VAR1 (GETREGP, get_dregoi, 0, ALL, di) - VAR1 (GETREGP, get_dregci, 0, ALL, di) - VAR1 (GETREGP, get_dregxi, 0, ALL, di) + BUILTIN_VDC (GETREG, get_dregoi, 0, AUTO_FP) + BUILTIN_VDC (GETREG, get_dregci, 0, AUTO_FP) + BUILTIN_VDC (GETREG, get_dregxi, 0, AUTO_FP) + VAR1 (GETREGP, get_dregoi, 0, AUTO_FP, di) + VAR1 (GETREGP, get_dregci, 0, AUTO_FP, di) + VAR1 (GETREGP, get_dregxi, 0, AUTO_FP, di) /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */ - BUILTIN_VQ (GETREG, get_qregoi, 0, ALL) - BUILTIN_VQ (GETREG, get_qregci, 0, ALL) - BUILTIN_VQ (GETREG, get_qregxi, 0, ALL) - VAR1 (GETREGP, get_qregoi, 0, ALL, v2di) - VAR1 (GETREGP, get_qregci, 0, ALL, v2di) - VAR1 (GETREGP, get_qregxi, 0, ALL, v2di) + BUILTIN_VQ (GETREG, get_qregoi, 0, AUTO_FP) + BUILTIN_VQ (GETREG, get_qregci, 0, AUTO_FP) + BUILTIN_VQ (GETREG, get_qregxi, 0, AUTO_FP) + VAR1 (GETREGP, get_qregoi, 0, AUTO_FP, v2di) + VAR1 (GETREGP, get_qregci, 0, AUTO_FP, v2di) + VAR1 (GETREGP, get_qregxi, 0, AUTO_FP, v2di) /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */ - BUILTIN_VQ (SETREG, set_qregoi, 0, ALL) - BUILTIN_VQ (SETREG, set_qregci, 0, ALL) - BUILTIN_VQ (SETREG, set_qregxi, 0, ALL) - VAR1 (SETREGP, set_qregoi, 0, ALL, v2di) - VAR1 (SETREGP, set_qregci, 0, ALL, v2di) - VAR1 (SETREGP, set_qregxi, 0, ALL, v2di) + BUILTIN_VQ (SETREG, set_qregoi, 0, AUTO_FP) + BUILTIN_VQ (SETREG, set_qregci, 0, AUTO_FP) + BUILTIN_VQ (SETREG, set_qregxi, 0, AUTO_FP) + VAR1 (SETREGP, set_qregoi, 0, AUTO_FP, v2di) + VAR1 (SETREGP, set_qregci, 0, AUTO_FP, v2di) + VAR1 (SETREGP, set_qregxi, 0, AUTO_FP, v2di) /* Implemented by aarch64_ld1x2<VQ:mode>. */ BUILTIN_VQ (LOADSTRUCT, ld1x2, 0, ALL) /* Implemented by aarch64_ld1x2<VDC:mode>. */ |