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author | Jeff Law <jlaw@ventanamicro> | 2023-05-06 13:28:33 -0600 |
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committer | Jeff Law <jlaw@ventanamicro> | 2023-05-06 13:49:38 -0600 |
commit | 4c05f966a098744db9fa1e73074d7c08ace446fd (patch) | |
tree | 6a19319b46273527a5492e96f33d04f5dae28901 | |
parent | 730909fa858bd691095bc23655077aa13b7941a9 (diff) | |
download | gcc-4c05f966a098744db9fa1e73074d7c08ace446fd.zip gcc-4c05f966a098744db9fa1e73074d7c08ace446fd.tar.gz gcc-4c05f966a098744db9fa1e73074d7c08ace446fd.tar.bz2 |
Delete duplicated riscv definition.
gcc/
* config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): Delete.
-rw-r--r-- | gcc/config/riscv/riscv-v.cc | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 9d699d4..8c7f320 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -190,44 +190,6 @@ autovec_use_vlmax_p (void) || riscv_autovec_preference == RVV_FIXED_VLMAX); } -/* Return the vectorization machine mode for RVV according to LMUL. */ -machine_mode -riscv_vector_preferred_simd_mode (scalar_mode mode) -{ - /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 && - riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE - when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. - in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have - VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are - enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to - use them. Currently, we can support auto-vectorization in - -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or - -march=rv32_zve32x_zvl64b are disabled. */ - if (autovec_use_vlmax_p ()) - { - /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2 - auto-vectorization since Loop Vectorizer may use VNx1SImode or - VNx1DImode to vectorize which will create ICE in the - 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. */ - if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2) - return word_mode; - /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and - riscv_autovec_lmul as multiply factor to calculate the the NUNITS to - get the auto-vectorization mode. */ - poly_uint64 nunits; - poly_uint64 vector_size - = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); - poly_uint64 scalar_size = GET_MODE_SIZE (mode); - gcc_assert (multiple_p (vector_size, scalar_size, &nunits)); - machine_mode rvv_mode; - if (get_vector_mode (mode, nunits).exists (&rvv_mode)) - return rvv_mode; - } - /* TODO: We will support minimum length VLS auto-vectorization in the future. - */ - return word_mode; -} - /* Emit an RVV unmask && vl mov from SRC to DEST. */ static void emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len, |