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author | Edwin Lu <ewlu@rivosinc.com> | 2023-08-29 08:30:10 -0700 |
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committer | Edwin Lu <ewlu@rivosinc.com> | 2023-08-29 08:30:10 -0700 |
commit | 4b70c7c849331d45c0d6a1a4e1cf96b103be9aa6 (patch) | |
tree | 3c075a732f2498d2245235070a13631de42e2963 | |
parent | 14a3839c63d550957556d70e824a8293938646e6 (diff) | |
download | gcc-4b70c7c849331d45c0d6a1a4e1cf96b103be9aa6.zip gcc-4b70c7c849331d45c0d6a1a4e1cf96b103be9aa6.tar.gz gcc-4b70c7c849331d45c0d6a1a4e1cf96b103be9aa6.tar.bz2 |
RISC-V: Add Types to Un-Typed Vector Instructions
Updates vector instructions to ensure that no instruction is left
without a type attribute. Create a placeholder type "vector" for
instructions where a type isn't clear
Tested for regressions using rv32/rv64 gc/gcv multilib with newlib/linux.
gcc/Changelog:
* config/riscv/autovec-vls.md: Update types
* config/riscv/riscv.md: Add vector placeholder type
* config/riscv/vector.md: Update types
Reviewed-by: Jeff Law <jlaw@ventanamicro.com>
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
-rw-r--r-- | gcc/config/riscv/autovec-vls.md | 15 | ||||
-rw-r--r-- | gcc/config/riscv/riscv.md | 3 | ||||
-rw-r--r-- | gcc/config/riscv/vector.md | 17 |
3 files changed, 26 insertions, 9 deletions
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index 1b1d940..35b86de 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -68,6 +68,7 @@ } DONE; } + [(set_attr "type" "vmov")] ) (define_insn_and_split "*mov<mode>" @@ -89,6 +90,7 @@ gcc_assert (ok_p); DONE; } + [(set_attr "type" "vmov")] ) (define_expand "mov<mode>" @@ -130,7 +132,9 @@ riscv_vector::RVV_UNOP, operands, operands[2]); } DONE; -}) +} + [(set_attr "type" "vmov")] +) (define_insn "*mov<mode>_vls" [(set (match_operand:VLS 0 "register_operand" "=vr") @@ -157,6 +161,7 @@ riscv_vector::RVV_UNOP, operands); DONE; } + [(set_attr "type" "vector")] ) ;; ------------------------------------------------------------------------- @@ -180,7 +185,9 @@ riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode), riscv_vector::RVV_BINOP, operands); DONE; -}) +} +[(set_attr "type" "vector")] +) ;; ------------------------------------------------------------------------------- ;; ---- [INT] Unary operations @@ -201,4 +208,6 @@ insn_code icode = code_for_pred (<CODE>, <MODE>mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands); DONE; -}) +} +[(set_attr "type" "vector")] +) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 87f4a4a..0127b9e 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -410,6 +410,7 @@ ;; vgather vector register gather instructions ;; vcompress vector compress instruction ;; vmov whole vector register move +;; vector unknown vector instruction (define_attr "type" "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -429,7 +430,7 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov" + vgather,vcompress,vmov,vector" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index d6bfbe8..27901c4 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -878,13 +878,15 @@ [(set (match_operand:V 0 "register_operand" "=vr") (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))] "TARGET_VECTOR" - "") + "" + [(set_attr "type" "vector")]) (define_insn "@vundefined<mode>" [(set (match_operand:VB 0 "register_operand" "=vr") (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))] "TARGET_VECTOR" - "") + "" + [(set_attr "type" "vector")]) (define_expand "@vreinterpret<mode>" [(set (match_operand:V 0 "register_operand") @@ -935,7 +937,8 @@ [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))] "TARGET_VECTOR" - "") + "" + [(set_attr "type" "vector")]) ;; Set VXRM (define_insn "vxrmsi" @@ -1135,7 +1138,9 @@ riscv_vector::RVV_UNOP, operands, operands[2]); } DONE; -}) +} +[(set_attr "type" "vector")] +) (define_insn_and_split "*mov<VB:mode><P:mode>_lra" [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr") @@ -1155,7 +1160,9 @@ riscv_vector::RVV_UNOP, operands, operands[2]); } DONE; -}) +} +[(set_attr "type" "vector")] +) ;; Define tuple modes data movement. ;; operands[2] is used to save the offset of each subpart. |