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| author | Haochen Jiang <haochen.jiang@intel.com> | 2024-01-09 14:59:30 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2024-01-11 11:28:08 +0800 |
| commit | 49a14ee488b8569abe318ca230ab115c36ca6b0c (patch) | |
| tree | fd8edb51ff81b2d37f0d2bc547f3db30ff4d0ffa | |
| parent | b4deb244dd2f4639b6f1c80d711215ca37e621df (diff) | |
| download | gcc-49a14ee488b8569abe318ca230ab115c36ca6b0c.zip gcc-49a14ee488b8569abe318ca230ab115c36ca6b0c.tar.gz gcc-49a14ee488b8569abe318ca230ab115c36ca6b0c.tar.bz2 | |
Add -mevex512 into invoke.texi
Hi Richard,
It seems that I send out a not updated patch. This patch should what
I want to send.
Thx,
Haochen
gcc/ChangeLog:
* doc/invoke.texi: Add -mevex512.
| -rw-r--r-- | gcc/doc/invoke.texi | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 216e2f5..3d2a711 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1463,7 +1463,7 @@ See RS/6000 and PowerPC Options. -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf --musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 +-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -35280,6 +35280,11 @@ To invoke egpr usage in inline asm, use new compiler option -mapx-inline-asm-use-gpr32 and user should ensure the instruction supports EGPR. +@opindex mevex512 +@item -mevex512 +@itemx -mno-evex512 +Enables/disables 512-bit vector. It will be default on if AVX512F is enabled. + @end table These @samp{-m} switches are supported in addition to the above |