RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1.

This patch adds testcase for form1, as shown below:

T __attribute__((noinline))                  \
sat_s_add_imm_##T##_fmt_1##_##INDEX (T x)             \
{                                            \
  T sum = (UT)x + (UT)IMM;                     \
  return (x ^ IMM) < 0                         \
    ? sum                                    \
    : (sum ^ x) >= 0                         \
      ? sum                                  \
      : x < 0 ? MIN : MAX;                   \
}

Passed the rv64gcv regression test.

Signed-off-by: Li Xu <xuli1@eswincomputing.com>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_s_add_imm-2.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1-i16.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-3.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1-i32.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-4.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1-i64.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1-i8.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-run-2.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-1-i16.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-run-3.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-1-i32.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-run-4.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-1-i64.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-run-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-1-i8.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-2-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i16.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-3-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i32.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-1-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i8.c: ...here.

11 files changed, 117 insertions, 4 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i16.c
index 3878286..2e23af5 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i16.c
@@ -29,4 +29,29 @@
 */
 DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -7, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
+/*
+** sat_s_add_imm_int16_t_fmt_1_1:
+** 	addi\s+[atx][0-9]+,\s*a0,\s*-1
+** 	not\s+[atx][0-9]+,\s*a0
+** 	xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** 	srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15
+** 	srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15
+** 	xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** 	and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** 	andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** 	srai\s+a0,\s*a0,\s*63
+** 	li\s+[atx][0-9]+,\s*32768
+** 	addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** 	xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** 	neg\s+a0,\s*[atx][0-9]+
+** 	and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** 	addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** 	and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** 	or\s+a0,\s*a0,\s*[atx][0-9]+
+** 	slliw\s+a0,\s*a0,\s*16
+** 	sraiw\s+a0,\s*a0,\s*16
+** 	ret
+*/
+DEF_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i32.c
index c9fbc66..e63211f 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i32.c
@@ -27,4 +27,28 @@
 */
 DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 10, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
+/*
+** sat_s_add_imm_int32_t_fmt_1_1:
+**	addi\s+[atx][0-9]+,\s*a0,\s*-1
+**	not\s+[atx][0-9]+,\s*a0
+**	xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+**	srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31
+**	srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31
+**	xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+**	and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+**	andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+**	srai\s+a0,\s*a0,\s*63
+**	li\s+[atx][0-9]+,\s*-2147483648
+**	xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+**	xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+**	neg\s+a0,\s*[atx][0-9]+
+**	and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+**	addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+**	and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+**	or\s+a0,\s*a0,\s*[atx][0-9]+
+**	sext.w\s+a0,\s*a0
+**	ret
+*/
+DEF_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i64.c
index 2aa9545..3843b71 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i64.c
@@ -25,4 +25,24 @@
 */
 DEF_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 10, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
+/*
+** sat_s_add_imm_int64_t_fmt_1_1:
+**	addi\s+[atx][0-9]+,\s*a0,\s*-1
+**	xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+**	srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
+**	slti\s+[atx][0-9]+,\s*a0,\s*0
+**	and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+**	srai\s+[atx][0-9]+,\s*a0,\s*63
+**	li\s+[atx][0-9]+,\s*-1
+**	srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+**	xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+**	neg\s+[atx][0-9]+,\s*[atx][0-9]+
+**	and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+**	addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+**	and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+**	or\s+a0,\s*a0,\s*[atx][0-9]+
+**	ret
+*/
+DEF_SAT_S_ADD_IMM_FMT_1(1, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i8.c
index b6f1731..ceae1ea 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i8.c
@@ -26,4 +26,24 @@
 */
 DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
+/*
+** sat_s_add_imm_int8_t_fmt_1_1:
+** 	addi\s+[atx][0-9]+,\s*a0,\s*-1
+** 	xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** 	and\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** 	slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*56
+** 	srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
+** 	srai\s+a0,\s*a0,\s*63
+** 	xori\s+[atx][0-9]+,\s*a0,\s*127
+** 	neg\s+a0,\s*a5
+** 	and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** 	addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** 	and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** 	or\s+a0,\s*a0,\s*[atx][0-9]+
+** 	slliw\s+a0,\s*a0,\s*24
+** 	sraiw\s+a0,\s*a0,\s*24
+** 	ret
+*/
+DEF_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i16.c
index 187a098..ae2c306 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i16.c
@@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -32768, INT16_MIN, INT16_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, 32767, INT16_MIN, INT16_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(2, int16_t, uint16_t, 100, INT16_MIN, INT16_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(3, int16_t, uint16_t, -100, INT16_MIN, INT16_MAX)
+DEF_SAT_S_ADD_IMM_FMT_1(4, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX)
 
 #define T                       int16_t
 #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect)
@@ -21,6 +22,8 @@ T d[][2] = {
   { -32768,     -32668, },
   { -32768,     -32768, },
   {      0,       -100, },
+  { -32768,     -32768, },
+  {      0,         -1, },
 };
 
 int
@@ -38,5 +41,8 @@ main ()
   RUN (3, T, d[6][0], d[6][1]);
   RUN (3, T, d[7][0], d[7][1]);
 
+  RUN (4, T, d[8][0], d[8][1]);
+  RUN (4, T, d[9][0], d[9][1]);
+
   return 0;
 }
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i32.c
index 899fda8..02a947f 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i32.c
@@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, -2147483648, INT32_MIN, INT32_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, 2147483647, INT32_MIN, INT32_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(2, int32_t, uint32_t, 100, INT32_MIN, INT32_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(3, int32_t, uint32_t, -100, INT32_MIN, INT32_MAX)
+DEF_SAT_S_ADD_IMM_FMT_1(4, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX)
 
 #define T                       int32_t
 #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect)
@@ -21,6 +22,8 @@ T d[][2] = {
   {   -300,            -200, },
   {    100,               0, },
   {      0,            -100, },
+  {    100,              99, },
+  {      0,              -1, },
 };
 
 int
@@ -38,5 +41,8 @@ main ()
   RUN (3, T, d[6][0], d[6][1]);
   RUN (3, T, d[7][0], d[7][1]);
 
+  RUN (4, T, d[8][0], d[8][1]);
+  RUN (4, T, d[9][0], d[9][1]);
+
   return 0;
 }
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i64.c
index 3dc4f72..40270ec 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i64.c
@@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, (-9223372036854775807ll - 1), INT6
 DEF_SAT_S_ADD_IMM_FMT_1(1, int64_t, uint64_t, 9223372036854775807ll, INT64_MIN, INT64_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(2, int64_t, uint64_t, 100, INT64_MIN, INT64_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(3, int64_t, uint64_t, -100, INT64_MIN, INT64_MAX)
+DEF_SAT_S_ADD_IMM_FMT_1(4, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX)
 
 #define T                       int64_t
 #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect)
@@ -21,6 +22,8 @@ T d[][2] = {
   {     -1,                               99, },
   {      0,                             -100, },
   {    100,                                0, },
+  {      0,                               -1, },
+  {    100,                               99, },
 };
 
 int
@@ -38,5 +41,8 @@ main ()
   RUN (3, T, d[6][0], d[6][1]);
   RUN (3, T, d[7][0], d[7][1]);
 
+  RUN (4, T, d[8][0], d[8][1]);
+  RUN (4, T, d[9][0], d[9][1]);
+
   return 0;
 }
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i8.c
index c71b717..9efb743 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i8.c
@@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, -128, INT8_MIN, INT8_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, 127, INT8_MIN, INT8_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(2, int8_t, uint8_t, 6, INT8_MIN, INT8_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(3, int8_t, uint8_t, -6, INT8_MIN, INT8_MAX)
+DEF_SAT_S_ADD_IMM_FMT_1(4, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX)
 
 #define T                       int8_t
 #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect)
@@ -21,6 +22,8 @@ T d[][2] = {
   {    -10,       -4, },
   {   -128,     -128, },
   {    127,      121, },
+  {   -128,     -128, },
+  {    1,          0, },
 };
 
 int
@@ -38,5 +41,8 @@ main ()
   RUN (3, T, d[6][0], d[6][1]);
   RUN (3, T, d[7][0], d[7][1]);
 
+  RUN (4, T, d[8][0], d[8][1]);
+  RUN (4, T, d[9][0], d[9][1]);
+
   return 0;
 }
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i16.c
index e9f7080..e9f7080 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i16.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i32.c
index 9dae425..9dae425 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i32.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i8.c
index 84c6bc7..84c6bc7 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i8.c