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| author | Bill Schmidt <wschmidt@vnet.linux.ibm.com> | 2013-07-24 13:17:31 +0000 |
|---|---|---|
| committer | William Schmidt <wschmidt@gcc.gnu.org> | 2013-07-24 13:17:31 +0000 |
| commit | 493f4c9e091a72c00b0b23f2e8ec137c4bde53ec (patch) | |
| tree | 78707a88fbda6d08a6211455fc74bb438ff907f2 | |
| parent | 017e07a1184c93792a0099b8ec1e242351ebe451 (diff) | |
| download | gcc-493f4c9e091a72c00b0b23f2e8ec137c4bde53ec.zip gcc-493f4c9e091a72c00b0b23f2e8ec137c4bde53ec.tar.gz gcc-493f4c9e091a72c00b0b23f2e8ec137c4bde53ec.tar.bz2 | |
vector.md (vec_realign_load_<mode>): Reorder input operands to vperm for little endian.
2013-07-24 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
Anton Blanchard <anton@au1.ibm.com>
* vector.md (vec_realign_load_<mode>): Reorder input operands to
vperm for little endian.
* rs6000.c (rs6000_expand_builtin): Use lvsr instead of lvsl to
create the control mask for a vperm for little endian.
Co-Authored-By: Anton Blanchard <anton@au1.ibm.com>
From-SVN: r201208
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 3 | ||||
| -rw-r--r-- | gcc/config/rs6000/vector.md | 8 |
3 files changed, 16 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 24e47d4..11a4830 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2013-07-24 Bill Schmidt <wschmidt@vnet.linux.ibm.com> + Anton Blanchard <anton@au1.ibm.com> + + * vector.md (vec_realign_load_<mode>): Reorder input operands to + vperm for little endian. + * rs6000.c (rs6000_expand_builtin): Use lvsr instead of lvsl to + create the control mask for a vperm for little endian. + 2013-07-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Anton Blanchard <anton@au1.ibm.com> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a3c9c98..8b939d8 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -12351,7 +12351,8 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case ALTIVEC_BUILTIN_MASK_FOR_LOAD: case ALTIVEC_BUILTIN_MASK_FOR_STORE: { - int icode = (int) CODE_FOR_altivec_lvsr; + int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr + : (int) CODE_FOR_altivec_lvsl); enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode = insn_data[icode].operand[1].mode; tree arg; diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 2eaa2d3..3faa798 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -936,8 +936,12 @@ (match_operand:V16QI 3 "vlogical_operand" "")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { - emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], operands[2], - operands[3])); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], + operands[2], operands[3])); + else + emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[2], + operands[1], operands[3])); DONE; }) |