testsuite: aarch64: arm: Enable vld1x?.c and vst1x?.c on arm [PR71233]

r14-7202-gc8ec3e1327cb1e added vld1xN and vst1xN intrinsics and some
tests on arm, but didn't enable some existing tests.

Since these tests are shared with aarch64, this patch removes the
'dg-skip-if "unimplemented" { arm*-*-* }' directives and relies on the
advsimd-intrinsics.exp driver to define the appropriate flags and
dg-do-what action.  (A previous patch removed 'dg-do run', and this
patch removes 'dg-options "-O3"' which would override the options
computed by the test driver)

float16 intrinsics require the neon-fp16 FPU, which is possibly
enabled by advsimd-intrinsics.exp, so we include them unconditionally
on aarch64 or if fp16 is enabled on arm.

poly64 intrinsics would require crypto-neon-fp-armv8: the patch
enables the corresponding tests on aarch64 only, since for arm they
are already covered by other tests in gcc.target/arm/simd/.  For some
reason, poly64 tests where missing from x2 and x3 tests, so the patch
adds them as needed.

Tested on aarch64-linux-gnu (no change), arm-linux-gnueabihf (the
additional tests are executed) and various flavors of arm-none-eabi
(the additional tests are compiled-only on M-profile, executed on
A-profile).

	gcc/testsuite/
	PR target/71233
	* gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: Enable on arm.
	* gcc.target/aarch64/advsimd-intrinsics/vld1x3.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x2.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x3.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x4.c: Likewise.

6 files changed, 90 insertions, 46 deletions

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
index 0892ce7..a653296 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
@@ -1,7 +1,3 @@
-/* We haven't implemented these intrinsics for arm yet.  */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
-/* { dg-options "-O3" } */
-
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
 
@@ -39,7 +35,6 @@ VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -51,17 +46,30 @@ VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+#if defined (__ARM_FP16_FORMAT_IEEE)	     \
+  || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \
+  || defined (__aarch64__)
+#define VARIANTS_F16(VARIANT)			\
+  VARIANT (float16, 4, _f16)			\
+  VARIANT (float16, 8, q_f16)
+#else
+#define VARIANTS_F16(VARIANTS_F16)
+#endif
+
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)				\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
 VARIANT (float64, 2, q_f64)
 #else
-#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)
 #endif
 
 /* Tests of vld1_x2 and vld1q_x2.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
index 9465e4a..832ee75 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
@@ -1,7 +1,3 @@
-/* We haven't implemented these intrinsics for arm yet.  */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
-/* { dg-options "-O3" } */
-
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
 
@@ -40,7 +36,6 @@ VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -52,17 +47,30 @@ VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+#if defined (__ARM_FP16_FORMAT_IEEE)	     \
+  || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \
+  || defined (__aarch64__)
+#define VARIANTS_F16(VARIANT)			\
+  VARIANT (float16, 4, _f16)			\
+  VARIANT (float16, 8, q_f16)
+#else
+#define VARIANTS_F16(VARIANTS_F16)
+#endif
+
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)				\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
 VARIANT (float64, 2, q_f64)
 #else
-#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)
 #endif
 
 
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
index a1461fd..e5f55f0 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
@@ -1,7 +1,3 @@
-/* We haven't implemented these intrinsics for arm yet.  */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
-/* { dg-options "-O3" } */
-
 #include <stdbool.h>
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
@@ -42,8 +38,6 @@ VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (poly64, 1, _p64)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -55,18 +49,30 @@ VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (poly64, 2, q_p64)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+#if defined (__ARM_FP16_FORMAT_IEEE)	     \
+  || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \
+  || defined (__aarch64__)
+#define VARIANTS_F16(VARIANT)			\
+  VARIANT (float16, 4, _f16)			\
+  VARIANT (float16, 8, q_f16)
+#else
+#define VARIANTS_F16(VARIANTS_F16)
+#endif
+
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)				\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
 VARIANT (float64, 2, q_f64)
 #else
-#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)
 #endif
 
 /* Tests of vld1_x4 and vld1q_x4.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
index 3cf5eb3..8399290 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
@@ -1,7 +1,3 @@
-/* We haven't implemented these intrinsics for arm yet.  */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
-/* { dg-options "-O3" } */
-
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
 
@@ -39,7 +35,6 @@ VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -51,17 +46,30 @@ VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+#if defined (__ARM_FP16_FORMAT_IEEE)	     \
+  || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \
+  || defined (__aarch64__)
+#define VARIANTS_F16(VARIANT)			\
+  VARIANT (float16, 4, _f16)			\
+  VARIANT (float16, 8, q_f16)
+#else
+#define VARIANTS_F16(VARIANTS_F16)
+#endif
+
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)				\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
 VARIANT (float64, 2, q_f64)
 #else
-#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)
 #endif
 
 /* Tests of vst1_x2 and vst1q_x2.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
index c05f8e7..e7d9e02 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
@@ -1,7 +1,3 @@
-/* We haven't implemented these intrinsics for arm yet.  */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
-/* { dg-options "-O3" } */
-
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
 
@@ -40,7 +36,6 @@ VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -52,17 +47,30 @@ VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+#if defined (__ARM_FP16_FORMAT_IEEE)	     \
+  || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \
+  || defined (__aarch64__)
+#define VARIANTS_F16(VARIANT)			\
+  VARIANT (float16, 4, _f16)			\
+  VARIANT (float16, 8, q_f16)
+#else
+#define VARIANTS_F16(VARIANTS_F16)
+#endif
+
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)				\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
 VARIANT (float64, 2, q_f64)
 #else
-#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)
 #endif
 
 /* Tests of vst1_x3 and vst1q_x3.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
index a9867c3..83b0567 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
@@ -1,7 +1,3 @@
-/* We haven't implemented these intrinsics for arm yet.  */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
-/* { dg-options "-O3" } */
-
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
 
@@ -41,8 +37,6 @@ VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (poly64, 1, _p64)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -54,18 +48,30 @@ VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (poly64, 2, q_p64)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+#if defined (__ARM_FP16_FORMAT_IEEE)	     \
+  || defined (__ARM_FP16_FORMAT_ALTERNATIVE) \
+  || defined (__aarch64__)
+#define VARIANTS_F16(VARIANT)			\
+  VARIANT (float16, 4, _f16)			\
+  VARIANT (float16, 8, q_f16)
+#else
+#define VARIANTS_F16(VARIANTS_F16)
+#endif
+
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)				\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
 VARIANT (float64, 2, q_f64)
 #else
-#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)
+#define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANTS_F16(VARIANT)
 #endif
 
 /* Tests of vst1_x4 and vst1q_x4.  */