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authorWilco Dijkstra <wdijkstr@arm.com>2016-11-02 13:56:07 +0000
committerWilco Dijkstra <wilco@gcc.gnu.org>2016-11-02 13:56:07 +0000
commit45a6c1e36347998df5e779866f26d15dc9d01fbd (patch)
treeeb8e76986eee365abe7bd9265d665197d978fd09
parentb5926e23e4721298fa9b81148cab86ee3042ea95 (diff)
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The add expander still contains some expansion code that was required for the previous prolog/epilog code...
The add expander still contains some expansion code that was required for the previous prolog/epilog code, but which is no longer needed. I also noticed that the current version splits off immediates from frame addressing instructions, which doesn't seem a good idea. Avoiding this resulted in small codesize improvements. gcc/ * config/aarch64/aarch64.md (add<mode>3): Remove redundant code. Don't split frame based additions. From-SVN: r241790
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/aarch64/aarch64.md25
2 files changed, 11 insertions, 19 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 054ed53..62211502 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-11-02 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.md (add<mode>3): Remove
+ redundant code. Don't split frame based additions.
+
2016-11-02 Richard Biener <rguenther@suse.de>
* gimple-ssa-store-merging.c (struct store_immediate_info): Remove
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 6afaf90..d5df9bb 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1605,25 +1605,12 @@
(match_operand:GPI 2 "aarch64_pluslong_operand" "")))]
""
{
- if (aarch64_pluslong_strict_immedate (operands[2], <MODE>mode))
- {
- /* Give CSE the opportunity to share this constant across additions. */
- if (!cse_not_expected && can_create_pseudo_p ())
- operands[2] = force_reg (<MODE>mode, operands[2]);
-
- /* Split will refuse to operate on a modification to the stack pointer.
- Aid the prologue and epilogue expanders by splitting this now. */
- else if (reload_completed && operands[0] == stack_pointer_rtx)
- {
- HOST_WIDE_INT i = INTVAL (operands[2]);
- HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
- emit_insn (gen_rtx_SET (operands[0],
- gen_rtx_PLUS (<MODE>mode, operands[1],
- GEN_INT (i - s))));
- operands[1] = operands[0];
- operands[2] = GEN_INT (s);
- }
- }
+ /* If the constant is too large for a single instruction and isn't frame
+ based, split off the immediate so it is available for CSE. */
+ if (!aarch64_plus_immediate (operands[2], <MODE>mode)
+ && can_create_pseudo_p ()
+ && !REGNO_PTR_FRAME_P (REGNO (operands[1])))
+ operands[2] = force_reg (<MODE>mode, operands[2]);
})
(define_insn "*add<mode>3_aarch64"