diff options
| author | David Edelsohn <dje.gcc@gmail.com> | 2016-04-29 17:20:36 +0000 |
|---|---|---|
| committer | David Edelsohn <dje@gcc.gnu.org> | 2016-04-29 13:20:36 -0400 |
| commit | 402315aee6f032bccf4aa5a007fce9c6cf80deae (patch) | |
| tree | 7ae26021b640ae730a9de187ef79cf214d95ec39 | |
| parent | f92ab29ffac7b8012c4787be66a43c08923c3663 (diff) | |
| download | gcc-402315aee6f032bccf4aa5a007fce9c6cf80deae.zip gcc-402315aee6f032bccf4aa5a007fce9c6cf80deae.tar.gz gcc-402315aee6f032bccf4aa5a007fce9c6cf80deae.tar.bz2 | |
re PR target/69810 (PowerPC64: unrecognizable insn)
PR target/69810
* config/rs6000/rs6000.md (EXTQI): Don't allow extension to HImode.
(zero_extendqi<mode>2_dot): Revert earlier conversion from
define_insn_and_split to define_insn.
(zero_extendqi<mode>2_dot2): Same.
(extendqi<mode>2_dot): Same.
(extendqi<mode>2_dot2): Same.
From-SVN: r235646
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 46 |
2 files changed, 47 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 01f2580..1b06c04 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2016-04-29 David Edelsohn <dje.gcc@gmail.com> + + PR target/69810 + * config/rs6000/rs6000.md (EXTQI): Don't allow extension to HImode. + (zero_extendqi<mode>2_dot): Revert earlier conversion from + define_insn_and_split to define_insn. + (zero_extendqi<mode>2_dot2): Same. + (extendqi<mode>2_dot): Same. + (extendqi<mode>2_dot2): Same. + 2016-04-29 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.md (unspec): Add UNSPEC_PROBE_STACK. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 849b19a..5566185 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -322,7 +322,7 @@ (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")]) ; Everything we can extend QImode to. -(define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")]) +(define_mode_iterator EXTQI [SI (DI "TARGET_POWERPC64")]) ; Everything we can extend HImode to. (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")]) @@ -711,7 +711,7 @@ rlwinm %0,%1,0,0xff" [(set_attr "type" "load,shift")]) -(define_insn "*zero_extendqi<mode>2_dot" +(define_insn_and_split "*zero_extendqi<mode>2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -719,12 +719,19 @@ "rs6000_gen_cell_microcode" "@ andi. %0,%1,0xff - rlwinm %0,%1,0,0xff\;cmpwi %2,%0,0" + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTQI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_insn "*zero_extendqi<mode>2_dot2" +(define_insn_and_split "*zero_extendqi<mode>2_dot2" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -733,7 +740,14 @@ "rs6000_gen_cell_microcode" "@ andi. %0,%1,0xff - rlwinm %0,%1,0,0xff\;cmpwi %2,%0,0" + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTQI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) @@ -851,7 +865,7 @@ "extsb %0,%1" [(set_attr "type" "exts")]) -(define_insn "*extendqi<mode>2_dot" +(define_insn_and_split "*extendqi<mode>2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -859,12 +873,19 @@ "rs6000_gen_cell_microcode" "@ extsb. %0,%1 - extsb %0,%1\;cmpwi %2,%0,0" + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (sign_extend:EXTQI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "exts") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_insn "*extendqi<mode>2_dot2" +(define_insn_and_split "*extendqi<mode>2_dot2" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -873,7 +894,14 @@ "rs6000_gen_cell_microcode" "@ extsb. %0,%1 - extsb %0,%1\;cmpwi %2,%0,0" + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (sign_extend:EXTQI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "exts") (set_attr "dot" "yes") (set_attr "length" "4,8")]) |