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| author | Richard Sandiford <richard.sandiford@arm.com> | 2020-01-06 13:00:04 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2020-01-06 13:00:04 +0000 |
| commit | 3c2707f33af46ac145769872b65e25fd0b870903 (patch) | |
| tree | bd94c4e46c475be1208574e7dc7df8f88ce61b59 | |
| parent | 5960de787f57b15dfbd76aa9fa40552a34ea9d9b (diff) | |
| download | gcc-3c2707f33af46ac145769872b65e25fd0b870903.zip gcc-3c2707f33af46ac145769872b65e25fd0b870903.tar.gz gcc-3c2707f33af46ac145769872b65e25fd0b870903.tar.bz2 | |
[AArch64] Fix constraints for CPY /M
The constraints for CPY /M allowed p0-p15 instead of the intended p0-p7.
This looks like a pasto from the preceding constant pattern, where p0-p15
is allowed.
2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
rather than Upa for CPY /M.
gcc/testsuite/
* gcc.target/aarch64/sve/acle/general/cpy_1.c: New test.
From-SVN: r279899
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c | 42 |
4 files changed, 52 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bd1c42e..520562a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-01-06 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl + rather than Upa for CPY /M. + 2020-01-06 Andrew Stubbs <ams@codesourcery.com> * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index cbf29a8..59bf4a6 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -6523,7 +6523,7 @@ (define_insn "@aarch64_sel_dup<mode>" [(set (match_operand:SVE_FULL 0 "register_operand" "=?w, w, ??w, ?&w, ??&w, ?&w") (unspec:SVE_FULL - [(match_operand:<VPRED> 3 "register_operand" "Upa, Upa, Upl, Upl, Upl, Upl") + [(match_operand:<VPRED> 3 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl") (vec_duplicate:SVE_FULL (match_operand:<VEL> 1 "register_operand" "r, w, r, w, r, w")) (match_operand:SVE_FULL 2 "aarch64_simd_reg_or_zero" "0, 0, Dz, Dz, w, w")] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 01d4022..878ea37 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-01-06 Richard Sandiford <richard.sandiford@arm.com> + + * gcc.target/aarch64/sve/acle/general/cpy_1.c: New test. + 2020-01-05 Andrew Pinski <apinski@marvell.com> * gcc.c-torture/compile/20200105-1.c: New testcase. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c new file mode 100644 index 0000000..1d8f429 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cpy_1.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include <arm_sve.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** dup_x0_m: +** add (x[0-9]+), x0, #?1 +** mov (p[0-7])\.b, p15\.b +** mov z0\.d, \2/m, \1 +** ret +*/ +svuint64_t +dup_x0_m (svuint64_t z0, uint64_t x0) +{ + register svbool_t pg asm ("p15"); + asm volatile ("" : "=Upa" (pg)); + return svdup_u64_m (z0, pg, x0 + 1); +} + +/* +** dup_d1_z: +** mov (p[0-7])\.b, p15\.b +** mov z0\.d, \1/m, d1 +** ret +*/ +svfloat64_t +dup_d1_z (svfloat64_t z0, float64_t d1) +{ + register svbool_t pg asm ("p15"); + asm volatile ("" : "=Upa" (pg)); + return svdup_f64_m (z0, pg, d1); +} + +#ifdef __cplusplus +} +#endif |