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| author | Andrew Stubbs <ams@codesourcery.com> | 2019-12-19 16:14:50 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@gcc.gnu.org> | 2019-12-19 16:14:50 +0000 |
| commit | 3a4d2bbc39e75feaf941a636f3de5057f3644380 (patch) | |
| tree | 8ae6f907367da3429d68e805307f48c934868bda | |
| parent | 8405874a0e2db1806332ead2dcf3e9ec563075aa (diff) | |
| download | gcc-3a4d2bbc39e75feaf941a636f3de5057f3644380.zip gcc-3a4d2bbc39e75feaf941a636f3de5057f3644380.tar.gz gcc-3a4d2bbc39e75feaf941a636f3de5057f3644380.tar.bz2 | |
Use V64SI for all amdgcn add-with-carry insns
2019-12-19 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (*plus_carry_dpp_shr_<mode>): Rename to ...
(*plus_carry_dpp_shr_v64si): ... this, and replace all
VEC_1REG_INT_MODE with V64SI.
From-SVN: r279584
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/gcn/gcn-valu.md | 14 |
2 files changed, 13 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 299f336..6340dea 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-12-19 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (*plus_carry_dpp_shr_<mode>): Rename to ... + (*plus_carry_dpp_shr_v64si): ... this, and replace all + VEC_1REG_INT_MODE with V64SI. + 2019-12-19 David Malcolm <dmalcolm@redhat.com> * hash-map-tests.c (selftest::test_map_of_int_to_strings): New diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 00a7604..369aae5 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -3075,18 +3075,18 @@ ; Special cases for addition. -(define_insn "*plus_carry_dpp_shr_<mode>" - [(set (match_operand:VEC_1REG_INT_MODE 0 "register_operand" "=v") - (unspec:VEC_1REG_INT_MODE - [(match_operand:VEC_1REG_INT_MODE 1 "register_operand" "v") - (match_operand:VEC_1REG_INT_MODE 2 "register_operand" "v") - (match_operand:SI 3 "const_int_operand" "n")] +(define_insn "*plus_carry_dpp_shr_v64si" + [(set (match_operand:V64SI 0 "register_operand" "=v") + (unspec:V64SI + [(match_operand:V64SI 1 "register_operand" "v") + (match_operand:V64SI 2 "register_operand" "v") + (match_operand:SI 3 "const_int_operand" "n")] UNSPEC_PLUS_CARRY_DPP_SHR)) (clobber (reg:DI VCC_REG))] "" { const char *insn = TARGET_GCN3 ? "v_add%u0" : "v_add_co%u0"; - return gcn_expand_dpp_shr_insn (<MODE>mode, insn, + return gcn_expand_dpp_shr_insn (V64SImode, insn, UNSPEC_PLUS_CARRY_DPP_SHR, INTVAL (operands[3])); } |