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| author | Tejas Belagod <tejas.belagod@arm.com> | 2025-04-13 01:08:00 +0530 |
|---|---|---|
| committer | Tejas Belagod <tejas.belagod@arm.com> | 2025-04-16 11:16:43 +0530 |
| commit | 31e16c8b75bd49a9c5c01ada340da340c6f15c99 (patch) | |
| tree | b1cf464d76c0f1c6790da0dd3c2a22607db66c1e | |
| parent | 43cbf049f5b017316f6fb1ea5f95784194323a51 (diff) | |
| download | gcc-31e16c8b75bd49a9c5c01ada340da340c6f15c99.zip gcc-31e16c8b75bd49a9c5c01ada340da340c6f15c99.tar.gz gcc-31e16c8b75bd49a9c5c01ada340da340c6f15c99.tar.bz2 | |
AArch64: Fix operands order in vec_extract expander
The operand order to gen_vcond_mask call in the vec_extract pattern is wrong.
Fix the order where predicate is operand 3.
Tested and bootstrapped on aarch64-linux-gnu. OK for trunk?
gcc/ChangeLog
* config/aarch64/aarch64-sve.md (vec_extract<vpred><Vel>): Fix operand
order to gen_vcond_mask_*.
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 3dbd659..d4af370 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3133,9 +3133,9 @@ "TARGET_SVE" { rtx tmp = gen_reg_rtx (<MODE>mode); - emit_insn (gen_vcond_mask_<mode><vpred> (tmp, operands[1], - CONST1_RTX (<MODE>mode), - CONST0_RTX (<MODE>mode))); + emit_insn (gen_vcond_mask_<mode><vpred> (tmp, CONST1_RTX (<MODE>mode), + CONST0_RTX (<MODE>mode), + operands[1])); emit_insn (gen_vec_extract<mode><Vel> (operands[0], tmp, operands[2])); DONE; } |