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author | Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> | 2022-07-30 04:32:46 +0900 |
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committer | Max Filippov <jcmvbkbc@gmail.com> | 2022-07-29 21:14:18 -0700 |
commit | 2fa8c4a659a19ec971c80704f48f96c13aae9ac3 (patch) | |
tree | 32c4de5bf7a2a033f0380b44c49baebb3fb94617 | |
parent | 48e9954d0865b5e5e31cb77ad05c45f7206eeb9f (diff) | |
download | gcc-2fa8c4a659a19ec971c80704f48f96c13aae9ac3.zip gcc-2fa8c4a659a19ec971c80704f48f96c13aae9ac3.tar.gz gcc-2fa8c4a659a19ec971c80704f48f96c13aae9ac3.tar.bz2 |
xtensa: Fix conflicting hard regno between indirect sibcall fixups and EH_RETURN_STACKADJ_RTX
The hard register A10 was already allocated for EH_RETURN_STACKADJ_RTX.
(although exception handling and sibling call may not apply at the same time,
but for safety)
gcc/ChangeLog:
* config/xtensa/xtensa.md: Change hard register number used in
the split patterns for indirect sibling call fixups from 10 to 11,
the last free one for the CALL0 ABI.
-rw-r--r-- | gcc/config/xtensa/xtensa.md | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 899ce27..1294aab 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -25,7 +25,7 @@ (A7_REG 7) (A8_REG 8) (A9_REG 9) - (A10_REG 10) + (A11_REG 11) (UNSPEC_NOP 2) (UNSPEC_PLT 3) @@ -2295,9 +2295,9 @@ "reload_completed && !TARGET_WINDOWED_ABI && SIBLING_CALL_P (insn) && ! call_used_or_fixed_reg_p (REGNO (operands[0]))" - [(set (reg:SI A10_REG) + [(set (reg:SI A11_REG) (match_dup 0)) - (call (mem:SI (reg:SI A10_REG)) + (call (mem:SI (reg:SI A11_REG)) (match_dup 1))]) (define_expand "sibcall_value" @@ -2328,10 +2328,10 @@ "reload_completed && !TARGET_WINDOWED_ABI && SIBLING_CALL_P (insn) && ! call_used_or_fixed_reg_p (REGNO (operands[1]))" - [(set (reg:SI A10_REG) + [(set (reg:SI A11_REG) (match_dup 1)) (set (match_dup 0) - (call (mem:SI (reg:SI A10_REG)) + (call (mem:SI (reg:SI A11_REG)) (match_dup 2)))]) (define_insn "entry" |