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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-11-07 22:45:05 +0800 |
|---|---|---|
| committer | Robin Dapp <rdapp@ventanamicro.com> | 2023-11-07 22:33:52 +0100 |
| commit | 2b61b8063b83c1764e43b547223372faee4bcfbd (patch) | |
| tree | ec6acd91a58cd49f09a3b6aacb65c9a3275a7f09 | |
| parent | fd940d248bfccb6994794152681dc4c693160919 (diff) | |
| download | gcc-2b61b8063b83c1764e43b547223372faee4bcfbd.zip gcc-2b61b8063b83c1764e43b547223372faee4bcfbd.tar.gz gcc-2b61b8063b83c1764e43b547223372faee4bcfbd.tar.bz2 | |
test: Recover sdiv_pow2 check and remove test of RISC-V
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-sdiv-pow2-1.c: Recover scan check.
* lib/target-supports.exp: Remove riscv.
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 4 |
2 files changed, 2 insertions, 4 deletions
diff --git a/gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c b/gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c index 8056c2a..49ecbe2 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c +++ b/gcc/testsuite/gcc.dg/vect/vect-sdiv-pow2-1.c @@ -79,5 +79,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump "vect_recog_divmod_pattern: detected" "vect" } } */ +/* { dg-final { scan-tree-dump {\.DIV_POW2} "vect" { target vect_sdiv_pow2_si } } } */ /* { dg-final { scan-tree-dump-times "vectorized 1 loop" 18 "vect" { target vect_sdiv_pow2_si } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 0317fc1..8f6cdf1 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -8077,9 +8077,7 @@ proc check_effective_target_vect_mulhrs_hi {} { proc check_effective_target_vect_sdiv_pow2_si {} { return [expr { ([istarget aarch64*-*-*] - && [check_effective_target_aarch64_sve]) - || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }] + && [check_effective_target_aarch64_sve]) }] } # Return 1 if the target plus current options supports a vector |