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| author | Richard Sandiford <richard.sandiford@arm.com> | 2020-04-15 13:52:20 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2020-04-16 15:45:37 +0100 |
| commit | 26bebf576ddcdcfb596f07e8c2896f17c48516e7 (patch) | |
| tree | df9a410eb6390626a266647b79738e148bc82e3a | |
| parent | d7a65edb629a010f7ef907d457343abcb569fab7 (diff) | |
| download | gcc-26bebf576ddcdcfb596f07e8c2896f17c48516e7.zip gcc-26bebf576ddcdcfb596f07e8c2896f17c48516e7.tar.gz gcc-26bebf576ddcdcfb596f07e8c2896f17c48516e7.tar.bz2 | |
aarch64: Fix mismatched SVE predicate modes [PR94606]
For this testcase we ended up generating the invalid rtl:
(insn 10 9 11 2 (set (reg:VNx16BI 105)
(and:VNx16BI (xor:VNx16BI (reg:VNx8BI 103)
(reg:VNx16BI 104))
(reg:VNx16BI 104))) "/tmp/bar.c":9:12 -1
(nil))
Fixed by taking the VNx16BI lowpart. It's safe to do that here because
the gp (r104) masks out the extra odd-indexed bits.
2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR target/94606
* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
the VNx16BI lowpart of the recursively-generated constant.
gcc/testsuite/
PR target/94606
* gcc.dg/vect/pr94606.c: New test.
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/pr94606.c | 13 |
4 files changed, 25 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9e499ec..0c7dad0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-04-16 Richard Sandiford <richard.sandiford@arm.com> + + PR target/94606 + * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take + the VNx16BI lowpart of the recursively-generated constant. + 2020-04-16 Martin Liska <mliska@suse.cz> Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 4af562a..d0a41c2 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4742,6 +4742,7 @@ aarch64_expand_sve_const_pred_eor (rtx target, rtx_vector_builder &builder, /* EOR the result with an ELT_SIZE PTRUE. */ rtx mask = aarch64_ptrue_all (elt_size); mask = force_reg (VNx16BImode, mask); + inv = gen_lowpart (VNx16BImode, inv); target = aarch64_target_reg (target, VNx16BImode); emit_insn (gen_aarch64_pred_z (XOR, VNx16BImode, target, mask, inv, mask)); return target; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 94d2312..72bed40 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-04-16 Richard Sandiford <richard.sandiford@arm.com> + + PR target/94606 + * gcc.dg/vect/pr94606.c: New test. + 2020-04-16 Martin Liska <mliska@suse.cz> Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/testsuite/gcc.dg/vect/pr94606.c b/gcc/testsuite/gcc.dg/vect/pr94606.c new file mode 100644 index 0000000..f0e7c4c --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr94606.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.2-a+sve -msve-vector-bits=256" { target aarch64*-*-* } } */ + +const short mask[] = { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 1, 1, 1, 1 }; + +int +foo (short *restrict x, short *restrict y) +{ + for (int i = 0; i < 16; ++i) + if (mask[i]) + x[i] += y[i]; +} |