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| author | Carl Love <cel@us.ibm.com> | 2017-11-13 22:40:18 +0000 |
|---|---|---|
| committer | Carl Love <carll@gcc.gnu.org> | 2017-11-13 22:40:18 +0000 |
| commit | 24cd339b9b17d7c26ce741bf3a72c5670cf7166d (patch) | |
| tree | 304f101568a9ee5005c56aea5670f7d493c55e14 | |
| parent | c1051bf7d8c99d056c6ae3353eb2b61751293d2f (diff) | |
| download | gcc-24cd339b9b17d7c26ce741bf3a72c5670cf7166d.zip gcc-24cd339b9b17d7c26ce741bf3a72c5670cf7166d.tar.gz gcc-24cd339b9b17d7c26ce741bf3a72c5670cf7166d.tar.bz2 | |
altivec.md (altivec_vsumsws_be): Add define_expand.
gcc/ChangeLog:
2017-11-13 Carl Love <cel@us.ibm.com>
* config/rs6000/altivec.md (altivec_vsumsws_be): Add define_expand.
gcc/testsuite/ChangeLog:
2017-11-13 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtin-vec-sums-be-int.c: New test file.
From-SVN: r254714
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-builtin.def | 1 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c | 16 |
4 files changed, 25 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b7ac84c..13a60e8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2017-11-13 Carl Love <cel@us.ibm.com> + + * config/rs6000/altivec.md (altivec_vsumsws_be): Add define_expand. + 2017-11-13 Tom Tromey <tom@tromey.com> * doc/cpp.texi (Variadic Macros): Document __VA_OPT__. diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 8eaa797..1ef98e3 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1079,6 +1079,7 @@ BU_ALTIVEC_2 (VSUM4SBS, "vsum4sbs", CONST, altivec_vsum4sbs) BU_ALTIVEC_2 (VSUM4SHS, "vsum4shs", CONST, altivec_vsum4shs) BU_ALTIVEC_2 (VSUM2SWS, "vsum2sws", CONST, altivec_vsum2sws) BU_ALTIVEC_2 (VSUMSWS, "vsumsws", CONST, altivec_vsumsws) +BU_ALTIVEC_2 (VSUMSWS_BE, "vsumsws_be", CONST, altivec_vsumsws_direct) BU_ALTIVEC_2 (VXOR, "vxor", CONST, xorv4si3) BU_ALTIVEC_2 (COPYSIGN_V4SF, "copysignfp", CONST, vector_copysignv4sf3) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b1c2f3e0..e522614 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-11-13 Carl Love <cel@us.ibm.com> + + * gcc.target/powerpc/builtin-vec-sums-be-int.c: New test file. + 2017-11-13 Tom Tromey <tom@tromey.com> * c-c++-common/cpp/va-opt-pedantic.c: New file. diff --git a/gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c b/gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c new file mode 100644 index 0000000..b4dfd06 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c @@ -0,0 +1,16 @@ +/* Test for the __builtin_altivec_vsumsws_be() builtin. + It produces just the instruction vsumsws in LE and BE modes. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include <altivec.h> + +vector signed int +test_vec_sums (vector signed int vsi2, vector signed int vsi3) +{ + return __builtin_altivec_vsumsws_be (vsi2, vsi3); +} + +/* { dg-final { scan-assembler-times "vsumsws" 1 } } */ |