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| author | ShiYulong <shiyulong@iscas.ac.cn> | 2022-05-10 11:25:24 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-05-24 21:00:33 +0800 |
| commit | 23c738bcba78a9df2259dd0626669c9a0aa04d1e (patch) | |
| tree | 8e91fb9143fe555b7b151a0e60f96ccfac50f6a2 | |
| parent | 4665cfbc4c70e24b4c885338577d4b7bc1752473 (diff) | |
| download | gcc-23c738bcba78a9df2259dd0626669c9a0aa04d1e.zip gcc-23c738bcba78a9df2259dd0626669c9a0aa04d1e.tar.gz gcc-23c738bcba78a9df2259dd0626669c9a0aa04d1e.tar.bz2 | |
RISC-V: Add mininal support for Zicbo[mzp]
This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions.
* config/riscv/riscv-opts.h (MASK_ZICBOZ): New.
(MASK_ZICBOM): New.
(MASK_ZICBOP): New.
(TARGET_ZICBOZ): New.
(TARGET_ZICBOM): New.
(TARGET_ZICBOP): New.
* config/riscv/riscv.opt (riscv_zicmo_subext): New.
| -rw-r--r-- | gcc/common/config/riscv/riscv-common.cc | 8 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-opts.h | 8 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.opt | 3 |
3 files changed, 19 insertions, 0 deletions
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 0b0ec2c..0e5be2c 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -165,6 +165,10 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1110,6 +1114,10 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH}, {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, + {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ}, + {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, + {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, + {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve64x", &gcc_options::x_target_flags, MASK_VECTOR}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 15bb5e7..1e153b3 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -145,6 +145,14 @@ enum stack_protector_guard { #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) +#define MASK_ZICBOZ (1 << 0) +#define MASK_ZICBOM (1 << 1) +#define MASK_ZICBOP (1 << 2) + +#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0) +#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0) +#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0) + /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use popcount to caclulate the minimal VLEN. */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 84c8cf5..9e9fe6d 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -209,6 +209,9 @@ int riscv_vector_elen_flags TargetVariable int riscv_zvl_flags +TargetVariable +int riscv_zicmo_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): |