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author | Uros Bizjak <ubizjak@gmail.com> | 2020-08-14 16:40:56 +0200 |
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committer | Uros Bizjak <ubizjak@gmail.com> | 2020-08-14 16:42:01 +0200 |
commit | 2398c206101f6da09f87e8afaf3ff422236db61d (patch) | |
tree | 8000e559c45a18b10bb5612e78f2dc984639cc7f | |
parent | 129a1319c0ab73f4bfc5598dffedb06378b00fc0 (diff) | |
download | gcc-2398c206101f6da09f87e8afaf3ff422236db61d.zip gcc-2398c206101f6da09f87e8afaf3ff422236db61d.tar.gz gcc-2398c206101f6da09f87e8afaf3ff422236db61d.tar.bz2 |
i386: Improve LWP builtin expanders.
Use parameterized pattern names to simplify calling of named patterns.
2020-08-14 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
* config/i386/i386-builtin.def (__builtin_ia32_llwpcb)
(__builtin_ia32_slwpcb, __builtin_ia32_lwpval32)
(__builtin_ia32_lwpval64, __builtin_ia32_lwpins32)
(__builtin_ia32_lwpins64): Use CODE_FOR_nothing.
* config/i386/i386.md (@lwp_llwpcb<mode>):
Implement as parametrized name pattern.
(@lwp_slwpcb<mode>): Ditto.
(@lwp_lwpval<mode>): Ditto.
(@lwp_lwpins<mode>): Ditto.
* config/i386/i386-expand.c (ix86_expand_special_args_builtin)
[case VOID_FTYPE_UINT_UINT_UINT, case VOID_FTYPE_UINT64_UINT_UINT]
[case UCHAR_FTYPE_UINT_UINT_UINT, case UCHAR_FTYPE_UINT64_UINT_UINT]:
Remove.
(ix86_expand_builtin)
[ case IX86_BUILTIN_LLWPCB, case IX86_BUILTIN_LLWPCB]:
Update for parameterized name patterns.
[case IX86_BUILTIN_LWPVAL32, case IX86_BUILTIN_LWPVAL64]
[case IX86_BUILTIN_LWPINS32, case IX86_BUILTIN_LWPINS64]: Expand here.
-rw-r--r-- | gcc/config/i386/i386-builtin.def | 12 | ||||
-rw-r--r-- | gcc/config/i386/i386-expand.c | 79 | ||||
-rw-r--r-- | gcc/config/i386/i386.md | 38 |
3 files changed, 67 insertions, 62 deletions
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 25b80868..3b6c4a8 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -260,12 +260,12 @@ BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_loadsf_mask, "__builtin_ia32 BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_storedf_mask, "__builtin_ia32_storesd_mask", IX86_BUILTIN_STORESD_MASK, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF_UQI) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_storesf_mask, "__builtin_ia32_storess_mask", IX86_BUILTIN_STORESS_MASK, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF_UQI) -BDESC (OPTION_MASK_ISA_LWP, 0, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID) -BDESC (OPTION_MASK_ISA_LWP, 0, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID) -BDESC (OPTION_MASK_ISA_LWP, 0, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT) -BDESC (OPTION_MASK_ISA_LWP | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT) -BDESC (OPTION_MASK_ISA_LWP, 0, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT) -BDESC (OPTION_MASK_ISA_LWP | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT) +BDESC (OPTION_MASK_ISA_LWP, 0, CODE_FOR_nothing, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID) +BDESC (OPTION_MASK_ISA_LWP, 0, CODE_FOR_nothing, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID) +BDESC (OPTION_MASK_ISA_LWP, 0, CODE_FOR_nothing, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT) +BDESC (OPTION_MASK_ISA_LWP | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT) +BDESC (OPTION_MASK_ISA_LWP, 0, CODE_FOR_nothing, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT) +BDESC (OPTION_MASK_ISA_LWP | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT) /* FSGSBASE */ BDESC (OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID) diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index aec894b..9de6f50 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -10665,15 +10665,6 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, klass = load; memory = 0; break; - case VOID_FTYPE_UINT_UINT_UINT: - case VOID_FTYPE_UINT64_UINT_UINT: - case UCHAR_FTYPE_UINT_UINT_UINT: - case UCHAR_FTYPE_UINT64_UINT_UINT: - nargs = 3; - klass = load; - memory = ARRAY_SIZE (args); - last_arg_constant = true; - break; default: gcc_unreachable (); } @@ -10728,13 +10719,7 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, { if (!match) { - if (icode == CODE_FOR_lwp_lwpvalsi3 - || icode == CODE_FOR_lwp_lwpinssi3 - || icode == CODE_FOR_lwp_lwpvaldi3 - || icode == CODE_FOR_lwp_lwpinsdi3) - error ("the last argument must be a 32-bit immediate"); - else - error ("the last argument must be an 8-bit immediate"); + error ("the last argument must be an 8-bit immediate"); return const0_rtx; } } @@ -11658,20 +11643,70 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, case IX86_BUILTIN_LLWPCB: arg0 = CALL_EXPR_ARG (exp, 0); op0 = expand_normal (arg0); - icode = CODE_FOR_lwp_llwpcb; - if (!insn_data[icode].operand[0].predicate (op0, Pmode)) + + if (!register_operand (op0, Pmode)) op0 = ix86_zero_extend_to_Pmode (op0); - emit_insn (gen_lwp_llwpcb (op0)); + emit_insn (gen_lwp_llwpcb (Pmode, op0)); return 0; case IX86_BUILTIN_SLWPCB: - icode = CODE_FOR_lwp_slwpcb; if (!target - || !insn_data[icode].operand[0].predicate (target, Pmode)) + || !register_operand (target, Pmode)) target = gen_reg_rtx (Pmode); - emit_insn (gen_lwp_slwpcb (target)); + emit_insn (gen_lwp_slwpcb (Pmode, target)); return target; + case IX86_BUILTIN_LWPVAL32: + case IX86_BUILTIN_LWPVAL64: + case IX86_BUILTIN_LWPINS32: + case IX86_BUILTIN_LWPINS64: + mode = ((fcode == IX86_BUILTIN_LWPVAL32 + || fcode == IX86_BUILTIN_LWPINS32) + ? SImode : DImode); + + if (fcode == IX86_BUILTIN_LWPVAL32 + || fcode == IX86_BUILTIN_LWPVAL64) + icode = code_for_lwp_lwpval (mode); + else + icode = code_for_lwp_lwpins (mode); + + arg0 = CALL_EXPR_ARG (exp, 0); + arg1 = CALL_EXPR_ARG (exp, 1); + arg2 = CALL_EXPR_ARG (exp, 2); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); + op2 = expand_normal (arg2); + mode0 = insn_data[icode].operand[0].mode; + + if (!insn_data[icode].operand[0].predicate (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + if (!insn_data[icode].operand[1].predicate (op1, SImode)) + op1 = copy_to_mode_reg (SImode, op1); + + if (!CONST_INT_P (op2)) + { + error ("the last argument must be a 32-bit immediate"); + return const0_rtx; + } + + emit_insn (GEN_FCN (icode) (op0, op1, op2)); + + if (fcode == IX86_BUILTIN_LWPINS32 + || fcode == IX86_BUILTIN_LWPINS64) + { + if (target == 0 + || !nonimmediate_operand (target, QImode)) + target = gen_reg_rtx (QImode); + + pat = gen_rtx_EQ (QImode, gen_rtx_REG (CCCmode, FLAGS_REG), + const0_rtx); + emit_insn (gen_rtx_SET (target, pat)); + + return target; + } + else + return 0; + case IX86_BUILTIN_BEXTRI32: case IX86_BUILTIN_BEXTRI64: arg0 = CALL_EXPR_ARG (exp, 0); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3985c77..bfc600c 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -21093,12 +21093,7 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "lwp_llwpcb" - [(unspec_volatile [(match_operand 0 "register_operand")] - UNSPECV_LLWP_INTRINSIC)] - "TARGET_LWP") - -(define_insn "*lwp_llwpcb<mode>_1" +(define_insn "@lwp_llwpcb<mode>" [(unspec_volatile [(match_operand:P 0 "register_operand" "r")] UNSPECV_LLWP_INTRINSIC)] "TARGET_LWP" @@ -21107,13 +21102,7 @@ (set_attr "mode" "<MODE>") (set_attr "length" "5")]) -(define_expand "lwp_slwpcb" - [(set (match_operand 0 "register_operand") - (unspec_volatile [(const_int 0)] UNSPECV_SLWP_INTRINSIC))] - "TARGET_LWP" - "emit_insn (gen_lwp_slwpcb_1 (Pmode, operands[0])); DONE;") - -(define_insn "@lwp_slwpcb<mode>_1" +(define_insn "@lwp_slwpcb<mode>" [(set (match_operand:P 0 "register_operand" "=r") (unspec_volatile:P [(const_int 0)] UNSPECV_SLWP_INTRINSIC))] "TARGET_LWP" @@ -21122,16 +21111,7 @@ (set_attr "mode" "<MODE>") (set_attr "length" "5")]) -(define_expand "lwp_lwpval<mode>3" - [(unspec_volatile [(match_operand:SWI48 1 "register_operand") - (match_operand:SI 2 "nonimmediate_operand") - (match_operand:SI 3 "const_int_operand")] - UNSPECV_LWPVAL_INTRINSIC)] - "TARGET_LWP" - ;; Avoid unused variable warning. - "(void) operands[0];") - -(define_insn "*lwp_lwpval<mode>3_1" +(define_insn "@lwp_lwpval<mode>" [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r") (match_operand:SI 1 "nonimmediate_operand" "rm") (match_operand:SI 2 "const_int_operand" "i")] @@ -21143,17 +21123,7 @@ (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 9"))]) -(define_expand "lwp_lwpins<mode>3" - [(set (reg:CCC FLAGS_REG) - (unspec_volatile:CCC [(match_operand:SWI48 1 "register_operand") - (match_operand:SI 2 "nonimmediate_operand") - (match_operand:SI 3 "const_int_operand")] - UNSPECV_LWPINS_INTRINSIC)) - (set (match_operand:QI 0 "nonimmediate_operand") - (eq:QI (reg:CCC FLAGS_REG) (const_int 0)))] - "TARGET_LWP") - -(define_insn "*lwp_lwpins<mode>3_1" +(define_insn "@lwp_lwpins<mode>" [(set (reg:CCC FLAGS_REG) (unspec_volatile:CCC [(match_operand:SWI48 0 "register_operand" "r") (match_operand:SI 1 "nonimmediate_operand" "rm") |