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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2014-09-12 09:42:42 +0000 |
|---|---|---|
| committer | Jiong Wang <jiwang@gcc.gnu.org> | 2014-09-12 09:42:42 +0000 |
| commit | 20b32e50e22de63de27708dfe50c5f51cb29eaac (patch) | |
| tree | edf33746a4b54fbaff2d193e35859d79aa464b0b | |
| parent | 3be0766211a509edfca09bb402706094c22e0921 (diff) | |
| download | gcc-20b32e50e22de63de27708dfe50c5f51cb29eaac.zip gcc-20b32e50e22de63de27708dfe50c5f51cb29eaac.tar.gz gcc-20b32e50e22de63de27708dfe50c5f51cb29eaac.tar.bz2 | |
[AArch64] Fix cost for Q register moves
2014-09-12 Wilco Dijkstra <wdijkstr@arm.com>
* gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
move handling.
(generic_regmove_cost): Undo raised FP2FP move cost as Q register moves are
now handled correctly.
From-SVN: r215207
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 7 |
2 files changed, 9 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 37202e8..b10f285 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2014-09-12 Wilco Dijkstra <wilco.dijkstra@arm.com> + * config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register + move handling. + (generic_regmove_cost): Undo raised FP2FP move cost as Q register moves + are now handled correctly. + +2014-09-12 Wilco Dijkstra <wilco.dijkstra@arm.com> + * config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost handling of CALLER_SAVE_REGS and POINTER_REGS. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 6f21fd9..73ddb0d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -215,10 +215,7 @@ static const struct cpu_regmove_cost generic_regmove_cost = NAMED_PARAM (GP2GP, 1), NAMED_PARAM (GP2FP, 2), NAMED_PARAM (FP2GP, 2), - /* We currently do not provide direct support for TFmode Q->Q move. - Therefore we need to raise the cost above 2 in order to have - reload handle the situation. */ - NAMED_PARAM (FP2FP, 4) + NAMED_PARAM (FP2FP, 2) }; /* Generic costs for vector insn classes. */ @@ -5961,7 +5958,7 @@ aarch64_register_move_cost (enum machine_mode mode, secondary reload. A general register is used as a scratch to move the upper DI value and the lower DI value is moved directly, hence the cost is the sum of three moves. */ - if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128) + if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 16) return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; return regmove_cost->FP2FP; |