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authorTobias Burnus <tburnus@baylibre.com>2025-04-15 23:19:50 +0200
committerTobias Burnus <tburnus@baylibre.com>2025-04-15 23:19:50 +0200
commit1ff4a22103767cd0133f0c1db6e85220f28ab3fa (patch)
tree6a7caa58fca57d61bfc280e56ef8d3bb59a9f160
parent727f330f9ac661339af1121fc5c9b67dd0d35872 (diff)
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libgomp.texi (gcn, nvptx): Mention self_maps alongside USM
libgomp/ChangeLog: * libgomp.texi (gcn, nvptx): Mention self_maps clause besides unified_shared_memory in the requirements item.
-rw-r--r--libgomp/libgomp.texi4
1 files changed, 2 insertions, 2 deletions
diff --git a/libgomp/libgomp.texi b/libgomp/libgomp.texi
index 3d3a56c..dfd189b 100644
--- a/libgomp/libgomp.texi
+++ b/libgomp/libgomp.texi
@@ -6888,7 +6888,7 @@ The implementation remark:
@code{device(ancestor:1)}) are processed serially per @code{target} region
such that the next reverse offload region is only executed after the previous
one returned.
-@item OpenMP code that has a @code{requires} directive with
+@item OpenMP code that has a @code{requires} directive with @code{self_maps} or
@code{unified_shared_memory} is only supported if all AMD GPUs have the
@code{HSA_AMD_SYSTEM_INFO_SVM_ACCESSIBLE_BY_DEFAULT} property; for
discrete GPUs, this may require setting the @code{HSA_XNACK} environment
@@ -7045,7 +7045,7 @@ The implementation remark:
Per device, reverse offload regions are processed serially such that
the next reverse offload region is only executed after the previous
one returned.
-@item OpenMP code that has a @code{requires} directive with
+@item OpenMP code that has a @code{requires} directive with @code{self_maps} or
@code{unified_shared_memory} runs on nvptx devices if and only if
all of those support the @code{pageableMemoryAccess} property;@footnote{
@uref{https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#um-requirements}}