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author | Richard Sandiford <rdsandiford@googlemail.com> | 2014-02-02 16:17:15 +0000 |
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committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2014-02-02 16:17:15 +0000 |
commit | 1ea0a6515f5f5da72f91ff5cfdc3723cf2b79507 (patch) | |
tree | 3b7c58c10699900c15fee4156f3368ce98a45a06 | |
parent | 70b2d364cc713fff51dcabfe987e3cb8efdcee93 (diff) | |
download | gcc-1ea0a6515f5f5da72f91ff5cfdc3723cf2b79507.zip gcc-1ea0a6515f5f5da72f91ff5cfdc3723cf2b79507.tar.gz gcc-1ea0a6515f5f5da72f91ff5cfdc3723cf2b79507.tar.bz2 |
configure.ac: Check __mips64 when setting host_address.
libgcc/
* configure.ac: Check __mips64 when setting host_address.
* configure: Regenerate.
* config.host (mips*-*-*): Add t-softfp-sfdf, mips/t-softfp-tf,
mips/t-mips64 and t-softfp.
(mips*-*-linux*): Don't add mips/t-tpbit.
* config/mips/t-mips (LIB2_SIDITI_CONV_FUNCS, FPBIT, FPBIT_CFLAGS)
(DPBIT, DPBIT_CFLAGS): Delete.
* config/mips/sfp-machine.h: New file.
* config/mips/t-mips64: Likewise.
* config/mips/t-softfp-tf: Likewise.
* config/mips/t-tpbit: Delete.
From-SVN: r207403
-rw-r--r-- | libgcc/ChangeLog | 14 | ||||
-rw-r--r-- | libgcc/config.host | 13 | ||||
-rw-r--r-- | libgcc/config/mips/sfp-machine.h | 178 | ||||
-rw-r--r-- | libgcc/config/mips/t-mips | 7 | ||||
-rw-r--r-- | libgcc/config/mips/t-mips64 | 1 | ||||
-rw-r--r-- | libgcc/config/mips/t-softfp-tf | 3 | ||||
-rw-r--r-- | libgcc/config/mips/t-tpbit | 4 | ||||
-rw-r--r-- | libgcc/configure | 6 | ||||
-rw-r--r-- | libgcc/configure.ac | 6 |
9 files changed, 213 insertions, 19 deletions
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index fe0f74d..58a8cad 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,17 @@ +2014-02-02 Richard Sandiford <rdsandiford@googlemail.com> + + * configure.ac: Check __mips64 when setting host_address. + * configure: Regenerate. + * config.host (mips*-*-*): Add t-softfp-sfdf, mips/t-softfp-tf, + mips/t-mips64 and t-softfp. + (mips*-*-linux*): Don't add mips/t-tpbit. + * config/mips/t-mips (LIB2_SIDITI_CONV_FUNCS, FPBIT, FPBIT_CFLAGS) + (DPBIT, DPBIT_CFLAGS): Delete. + * config/mips/sfp-machine.h: New file. + * config/mips/t-mips64: Likewise. + * config/mips/t-softfp-tf: Likewise. + * config/mips/t-tpbit: Delete. + 2014-01-29 Marcus Shawcroft <marcus.shawcroft@arm.com> * config/aarch64/sfp-machine.h (_FP_I_TYPE): Define diff --git a/libgcc/config.host b/libgcc/config.host index 65f6b0f..cc7becf 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -140,8 +140,16 @@ microblaze*-*-*) cpu_type=microblaze ;; mips*-*-*) + # All MIPS targets provide a full set of FP routines. cpu_type=mips - tmake_file=mips/t-mips + tmake_file="mips/t-mips t-softfp-sfdf" + if test "${ac_cv_sizeof_long_double}" = 16; then + tmake_file="${tmake_file} mips/t-softfp-tf" + fi + if test "${host_address}" = 64; then + tmake_file="${tmake_file} mips/t-mips64" + fi + tmake_file="${tmake_file} t-softfp" ;; nds32*-*) cpu_type=nds32 @@ -776,9 +784,6 @@ mips*-*-linux*) # Linux MIPS, either endian. ;; esac md_unwind_header=mips/linux-unwind.h - if test "${ac_cv_sizeof_long_double}" = 16; then - tmake_file="${tmake_file} mips/t-tpbit" - fi ;; mips*-sde-elf*) tmake_file="$tmake_file mips/t-crtstuff mips/t-mips16" diff --git a/libgcc/config/mips/sfp-machine.h b/libgcc/config/mips/sfp-machine.h new file mode 100644 index 0000000..808570e --- /dev/null +++ b/libgcc/config/mips/sfp-machine.h @@ -0,0 +1,178 @@ +/* softfp machine description for MIPS. + Copyright (C) 2009-2014 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#ifdef __mips64 +#define _FP_W_TYPE_SIZE 64 +#define _FP_W_TYPE unsigned long long +#define _FP_WS_TYPE signed long long +#define _FP_I_TYPE long long + +typedef int TItype __attribute__ ((mode (TI))); +typedef unsigned int UTItype __attribute__ ((mode (TI))); +#define TI_BITS (__CHAR_BIT__ * (int) sizeof (TItype)) + +#define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_D(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_Q(R,X,Y) \ + _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) + +#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(S,R,X,Y) +#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y) +#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) + +#ifdef __mips_nan2008 +# define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +# define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1) +# define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1 +#else +# define _FP_NANFRAC_S (_FP_QNANBIT_S - 1) +# define _FP_NANFRAC_D (_FP_QNANBIT_D - 1) +# define _FP_NANFRAC_Q (_FP_QNANBIT_Q - 1), -1 +#endif +#else +#define _FP_W_TYPE_SIZE 32 +#define _FP_W_TYPE unsigned int +#define _FP_WS_TYPE signed int +#define _FP_I_TYPE int + +#define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_D(R,X,Y) \ + _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_Q(R,X,Y) \ + _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) + +#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(S,R,X,Y) +#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) +#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) + +#ifdef __mips_nan2008 +# define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +# define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 +# define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 +#else +# define _FP_NANFRAC_S (_FP_QNANBIT_S - 1) +# define _FP_NANFRAC_D (_FP_QNANBIT_D - 1), -1 +# define _FP_NANFRAC_Q (_FP_QNANBIT_Q - 1), -1, -1, -1 +#endif +#endif + +/* The type of the result of a floating point comparison. This must + match __libgcc_cmp_return__ in GCC for the target. */ +typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); +#define CMPtype __gcc_CMPtype + +#define _FP_NANSIGN_S 0 +#define _FP_NANSIGN_D 0 +#define _FP_NANSIGN_Q 0 + +#define _FP_KEEPNANFRACP 1 +#ifdef __mips_nan2008 +# define _FP_QNANNEGATEDP 0 +#else +# define _FP_QNANNEGATEDP 1 +#endif + +/* Comment from glibc: */ +/* From my experiments it seems X is chosen unless one of the + NaNs is sNaN, in which case the result is NANSIGN/NANFRAC. */ +#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ + do { \ + if ((_FP_FRAC_HIGH_RAW_##fs(X) | \ + _FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs) \ + { \ + R##_s = _FP_NANSIGN_##fs; \ + _FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \ + } \ + else \ + { \ + R##_s = X##_s; \ + _FP_FRAC_COPY_##wc(R,X); \ + } \ + R##_c = FP_CLS_NAN; \ + } while (0) + +#ifdef __mips_hard_float +#define FP_EX_INVALID 0x40 +#define FP_EX_DIVZERO 0x20 +#define FP_EX_OVERFLOW 0x10 +#define FP_EX_UNDERFLOW 0x08 +#define FP_EX_INEXACT 0x04 +#define FP_EX_ALL \ + (FP_EX_INVALID | FP_EX_DIVZERO | FP_EX_OVERFLOW | FP_EX_UNDERFLOW \ + | FP_EX_INEXACT) + +#define FP_EX_ENABLE_SHIFT 5 +#define FP_EX_CAUSE_SHIFT 10 + +#define FP_RND_NEAREST 0x0 +#define FP_RND_ZERO 0x1 +#define FP_RND_PINF 0x2 +#define FP_RND_MINF 0x3 +#define FP_RND_MASK 0x3 + +#define _FP_DECL_EX \ + unsigned long int _fcsr __attribute__ ((unused)) = FP_RND_NEAREST + +#define FP_INIT_ROUNDMODE \ + do { \ + _fcsr = __builtin_mips_get_fcsr (); \ + } while (0) + +#define FP_ROUNDMODE (_fcsr & FP_RND_MASK) + +#define FP_TRAPPING_EXCEPTIONS ((_fcsr >> FP_EX_ENABLE_SHIFT) & FP_EX_ALL) + +#define FP_HANDLE_EXCEPTIONS \ + do { \ + _fcsr &= ~(FP_EX_ALL << FP_EX_CAUSE_SHIFT); \ + /* Also clear Unimplemented Operation. */ \ + _fcsr &= ~(1 << 17); \ + _fcsr |= _fex | (_fex << FP_EX_CAUSE_SHIFT); \ + __builtin_mips_set_fcsr (_fcsr); \ + } while (0); + +#else +#define FP_EX_INVALID (1 << 4) +#define FP_EX_DIVZERO (1 << 3) +#define FP_EX_OVERFLOW (1 << 2) +#define FP_EX_UNDERFLOW (1 << 1) +#define FP_EX_INEXACT (1 << 0) +#endif + +#define __LITTLE_ENDIAN 1234 +#define __BIG_ENDIAN 4321 + +#if defined _MIPSEB +# define __BYTE_ORDER __BIG_ENDIAN +#else +# define __BYTE_ORDER __LITTLE_ENDIAN +#endif + +/* Define ALIASNAME as a strong alias for NAME. */ +# define strong_alias(name, aliasname) _strong_alias(name, aliasname) +# define _strong_alias(name, aliasname) \ + extern __typeof (name) aliasname __attribute__ ((alias (#name))); diff --git a/libgcc/config/mips/t-mips b/libgcc/config/mips/t-mips index ed5550e..4f94ee6 100644 --- a/libgcc/config/mips/t-mips +++ b/libgcc/config/mips/t-mips @@ -1,8 +1 @@ -LIB2_SIDITI_CONV_FUNCS = yes - -FPBIT = true -FPBIT_CFLAGS = -DQUIET_NAN_NEGATED -DPBIT = true -DPBIT_CFLAGS = -DQUIET_NAN_NEGATED - LIB2ADD_ST += $(srcdir)/config/mips/lib2funcs.c diff --git a/libgcc/config/mips/t-mips64 b/libgcc/config/mips/t-mips64 new file mode 100644 index 0000000..a1e3513 --- /dev/null +++ b/libgcc/config/mips/t-mips64 @@ -0,0 +1 @@ +softfp_int_modes += ti diff --git a/libgcc/config/mips/t-softfp-tf b/libgcc/config/mips/t-softfp-tf new file mode 100644 index 0000000..306677b --- /dev/null +++ b/libgcc/config/mips/t-softfp-tf @@ -0,0 +1,3 @@ +softfp_float_modes += tf +softfp_extensions += sftf dftf +softfp_truncations += tfsf tfdf diff --git a/libgcc/config/mips/t-tpbit b/libgcc/config/mips/t-tpbit deleted file mode 100644 index 1670ef3..0000000 --- a/libgcc/config/mips/t-tpbit +++ /dev/null @@ -1,4 +0,0 @@ -ifeq ($(long_double_type_size),128) -TPBIT = true -TPBIT_CFLAGS = -DQUIET_NAN_NEGATED -endif diff --git a/libgcc/configure b/libgcc/configure index 7e177ed..092e20e 100644 --- a/libgcc/configure +++ b/libgcc/configure @@ -4317,9 +4317,11 @@ fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_cfi" >&5 $as_echo "$libgcc_cv_cfi" >&6; } -# Check 32bit or 64bit +# Check 32bit or 64bit. In the case of MIPS, this really determines the +# word size rather than the address size. cat > conftest.c <<EOF -#if defined(__x86_64__) || (!defined(__i386__) && defined(__LP64__)) +#if defined(__x86_64__) || (!defined(__i386__) && defined(__LP64__)) \ + || defined(__mips64) host_address=64 #else host_address=32 diff --git a/libgcc/configure.ac b/libgcc/configure.ac index 560e988..d77a8f0 100644 --- a/libgcc/configure.ac +++ b/libgcc/configure.ac @@ -279,9 +279,11 @@ AC_CACHE_CHECK([whether assembler supports CFI directives], [libgcc_cv_cfi], [libgcc_cv_cfi=yes], [libgcc_cv_cfi=no])]) -# Check 32bit or 64bit +# Check 32bit or 64bit. In the case of MIPS, this really determines the +# word size rather than the address size. cat > conftest.c <<EOF -#if defined(__x86_64__) || (!defined(__i386__) && defined(__LP64__)) +#if defined(__x86_64__) || (!defined(__i386__) && defined(__LP64__)) \ + || defined(__mips64) host_address=64 #else host_address=32 |