i386.md (all XFmode patterns except swapxf): Disable for 64bit.

	* i386.md (all XFmode patterns except swapxf): Disable for 64bit.

	* i386.md (x86_sahf_1): Disable for 64bit.
	(popsi*, pophi*): Likewise.
	(pushqi, pushhi): Likewise.
	(movdi, pushdi): Likewise.
	(zero extend DImode splitter): Likewise.
	(adddi, minusdi splitter): Likewise.
	(umulsidi): Likewise.
	(umulsi): New.
	(mulsidi): Disable for 64bit
	(lshift:DI/ashift:DI): Disable for 64bit.
	(loop patterns): Likewise.
	(call_pop, call_value_pop expanders and patterns): Likewise.
	(prologue_get_pc): Likewise.
	(leave): Likewise.
	(fcmovDI pattern and splitter): Likewise.
	(movdfcc_1_rex64): New.

From-SVN: r40412

2 files changed, 147 insertions, 87 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cf724ab..7513089 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+Mon Mar 12 15:41:08 CET 2001  Jan Hubicka  <jh@suse.cz>
+
+	* i386.md (all XFmode patterns except swapxf): Disable for 64bit.
+
+	* i386.md (x86_sahf_1): Disable for 64bit.
+	(popsi*, pophi*): Likewise.
+	(pushqi, pushhi): Likewise.
+	(movdi, pushdi): Likewise.
+	(zero extend DImode splitter): Likewise.
+	(adddi, minusdi splitter): Likewise.
+	(umulsidi): Likewise.
+	(umulsi): New.
+	(mulsidi): Disable for 64bit
+	(lshift:DI/ashift:DI): Disable for 64bit.
+	(loop patterns): Likewise.
+	(call_pop, call_value_pop expanders and patterns): Likewise.
+	(prologue_get_pc): Likewise.
+	(leave): Likewise.
+	(fcmovDI pattern and splitter): Likewise.
+	(movdfcc_1_rex64): New.
+
 Mon Mar 12 15:16:36 CET 2001  Jan Hubicka  <jh@suse.cz>
 
 	* i386.h (VALID_FP_MODE_P): XFmode is invalid on x86_64.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index b350729..735f472 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1273,7 +1273,7 @@
   [(set (reg:CC 17)
 	(compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
 		    (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "
 {
   ix86_compare_op0 = operands[0];
@@ -1403,7 +1403,7 @@
 	(compare:CCFP
 	  (match_operand:XF 0 "register_operand" "f")
 	  (match_operand:XF 1 "register_operand" "f")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "* return output_fp_compare (insn, operands, 0, 0);"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "XF")])
@@ -1424,7 +1424,7 @@
 	  [(compare:CCFP
 	     (match_operand:XF 1 "register_operand" "f")
 	     (match_operand:XF 2 "register_operand" "f"))] 9))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "* return output_fp_compare (insn, operands, 2, 0);"
   [(set_attr "type" "multi")
    (set_attr "mode" "XF")])
@@ -1519,7 +1519,7 @@
 (define_insn "x86_sahf_1"
   [(set (reg:CC 17)
 	(unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
-  ""
+  "!TARGET_64BIT"
   "sahf"
   [(set_attr "length" "1")
    (set_attr "athlon_decode" "vector")
@@ -1642,7 +1642,7 @@
    (set (reg:SI 7)
 	(plus:SI (reg:SI 7) (const_int 4)))
    (set (reg:SI 6) (reg:SI 6))]
-  ""
+  "!TARGET_64BIT"
   "pop{l}\\t%0"
   [(set_attr "type" "pop")
    (set_attr "mode" "SI")])
@@ -1652,7 +1652,7 @@
 	(mem:SI (reg:SI 7)))
    (set (reg:SI 7)
 	(plus:SI (reg:SI 7) (const_int 4)))]
-  ""
+  "!TARGET_64BIT"
   "pop{l}\\t%0"
   [(set_attr "type" "pop")
    (set_attr "mode" "SI")])
@@ -1738,7 +1738,7 @@
 (define_insn "*pushhi2"
   [(set (match_operand:HI 0 "push_operand" "=<,<")
 	(match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
-  ""
+  "!TARGET_64BIT"
   "@
    push{w}\\t{|WORD PTR }%1
    push{w}\\t%1"
@@ -1750,7 +1750,7 @@
 	(mem:HI (reg:SI 7)))
    (set (reg:SI 7)
 	(plus:SI (reg:SI 7) (const_int 2)))]
-  ""
+  "!TARGET_64BIT"
   "pop{w}\\t%0"
   [(set_attr "type" "pop")
    (set_attr "mode" "HI")])
@@ -1875,7 +1875,7 @@
 (define_insn "*pushqi2"
   [(set (match_operand:QI 0 "push_operand" "=<,<")
 	(match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
-  ""
+  "!TARGET_64BIT"
   "@
    push{w}\\t{|word ptr }%1
    push{w}\\t%w1"
@@ -1887,7 +1887,7 @@
 	(mem:QI (reg:SI 7)))
    (set (reg:SI 7)
 	(plus:SI (reg:SI 7) (const_int 2)))]
-  ""
+  "!TARGET_64BIT"
   "pop{w}\\t%0"
   [(set_attr "type" "pop")
    (set_attr "mode" "HI")])
@@ -2177,13 +2177,14 @@
 (define_insn "*pushdi"
   [(set (match_operand:DI 0 "push_operand" "=<")
 	(match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
-  ""
+  "!TARGET_64BIT"
   "#")
 
 (define_insn "*movdi_2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y")
 	(match_operand:DI 1 "general_operand" "riFo,riF,*y,m"))]
-  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
+  "!TARGET_64BIT
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "@
    #
    #
@@ -2194,7 +2195,7 @@
 (define_split
   [(set (match_operand:DI 0 "push_operand" "")
         (match_operand:DI 1 "general_operand" ""))]
-  "reload_completed && ! MMX_REG_P (operands[1])"
+  "reload_completed && ! MMX_REG_P (operands[1]) && !TARGET_64BIT"
   [(const_int 0)]
   "if (!ix86_split_long_move (operands)) abort (); DONE;")
 
@@ -2577,7 +2578,7 @@
 (define_expand "movxf"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
 	(match_operand:XF 1 "general_operand" ""))]
-  ""
+  "!TARGET_64BIT"
   "ix86_expand_move (XFmode, operands); DONE;")
 
 (define_expand "movtf"
@@ -2594,9 +2595,9 @@
 ;;  handled elsewhere).
 
 (define_insn "*pushxf_nointeger"
-  [(set (match_operand:XF 0 "push_operand" "=<,<,<")
+  [(set (match_operand:XF 0 "push_operand" "=X,X,X")
 	(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
-  "optimize_size"
+  "optimize_size && !TARGET_64BIT"
   "*
 {
   switch (which_alternative)
@@ -2653,8 +2654,8 @@
 
 (define_insn "*pushxf_integer"
   [(set (match_operand:XF 0 "push_operand" "=<,<")
-	(match_operand:XF 1 "general_no_elim_operand" "f#r,rFo#f"))]
-  "!optimize_size"
+	(match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
+  "!optimize_size && !TARGET_64BIT"
   "*
 {
   switch (which_alternative)
@@ -2737,6 +2738,7 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
 	(match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
   "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
+   && !TARGET_64BIT
    && optimize_size
    && (reload_in_progress || reload_completed
        || GET_CODE (operands[1]) != CONST_DOUBLE
@@ -2831,6 +2833,7 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
 	(match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
   "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
+   && !TARGET_64BIT
    && !optimize_size
    && (reload_in_progress || reload_completed
        || GET_CODE (operands[1]) != CONST_DOUBLE
@@ -3187,7 +3190,8 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(zero_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])"
+  "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])
+   && !TARGET_64BIT"
   [(set (match_dup 4) (const_int 0))]
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
 
@@ -3475,7 +3479,7 @@
 (define_expand "extendsfxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
         (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
@@ -3485,7 +3489,7 @@
 (define_insn "*extendsfxf2_1"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
         (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
-  "TARGET_80387
+  "TARGET_80387 && !TARGET_64BIT
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "*
 {
@@ -3561,7 +3565,7 @@
 (define_expand "extenddfxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
         (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
@@ -3571,7 +3575,7 @@
 (define_insn "*extenddfxf2_1"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
         (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
-  "TARGET_80387
+  "TARGET_80387 && !TARGET_64BIT
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "*
 {
@@ -3795,7 +3799,7 @@
 		   (float_truncate:SF
 		    (match_operand:XF 1 "register_operand" "")))
 	      (clobber (match_dup 2))])]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "operands[2] = assign_386_stack_local (SFmode, 0);")
 
 (define_insn "*truncxfsf2_1"
@@ -3803,7 +3807,7 @@
 	(float_truncate:SF
 	 (match_operand:XF 1 "register_operand" "f,0")))
    (clobber (match_operand:SF 2 "memory_operand" "=m,m"))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "*
 {
   switch (which_alternative)
@@ -3825,7 +3829,7 @@
   [(set (match_operand:SF 0 "memory_operand" "=m")
 	(float_truncate:SF
 	 (match_operand:XF 1 "register_operand" "f")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "*
 {
   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
@@ -3886,7 +3890,7 @@
   [(set_attr "type" "fmov,multi")
    (set_attr "mode" "SF")])
 
-(define_insn "*truncxfsf2_2"
+(define_insn "*trunctfsf2_2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=m")
 	(float_truncate:SF
 	 (match_operand:TF 1 "register_operand" "f")))]
@@ -3926,7 +3930,7 @@
 		   (float_truncate:DF
 		    (match_operand:XF 1 "register_operand" "")))
 	      (clobber (match_dup 2))])]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "operands[2] = assign_386_stack_local (DFmode, 0);")
 
 (define_insn "*truncxfdf2_1"
@@ -3934,7 +3938,7 @@
 	(float_truncate:DF
 	 (match_operand:XF 1 "register_operand" "f,0")))
    (clobber (match_operand:DF 2 "memory_operand" "=m,m"))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "*
 {
   switch (which_alternative)
@@ -3956,7 +3960,7 @@
   [(set (match_operand:DF 0 "memory_operand" "=m")
 	(float_truncate:DF
 	  (match_operand:XF 1 "register_operand" "f")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "*
 {
   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
@@ -4063,7 +4067,7 @@
 	      (clobber (match_dup 3))
 	      (clobber (match_scratch:SI 4 ""))
 	      (clobber (match_scratch:XF 5 ""))])]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "operands[2] = assign_386_stack_local (SImode, 0);
    operands[3] = assign_386_stack_local (DImode, 1);")
 
@@ -4135,7 +4139,7 @@
 	      (clobber (match_dup 2))
 	      (clobber (match_dup 3))
 	      (clobber (match_scratch:SI 4 ""))])]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "operands[2] = assign_386_stack_local (SImode, 0);
    operands[3] = assign_386_stack_local (SImode, 1);")
 
@@ -4449,7 +4453,7 @@
 (define_insn "floathixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "@
    fild%z1\\t%1
    #"
@@ -4471,7 +4475,7 @@
 (define_insn "floatsixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "@
    fild%z1\\t%1
    #"
@@ -4493,7 +4497,7 @@
 (define_insn "floatdixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "@
    fild%z1\\t%1
    #"
@@ -4549,7 +4553,7 @@
 	(plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
 		 (match_operand:DI 2 "general_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed"
+  "reload_completed && !TARGET_64BIT"
   [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
 	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
    (parallel [(set (match_dup 3)
@@ -5598,7 +5602,7 @@
   [(set (match_operand:XF 0 "register_operand" "")
 	(plus:XF (match_operand:XF 1 "register_operand" "")
 		 (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "")
 
 (define_expand "addtf3"
@@ -5640,7 +5644,7 @@
 	(minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
 		  (match_operand:DI 2 "general_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed"
+  "reload_completed && !TARGET_64BIT"
   [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
 	      (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
    (parallel [(set (match_dup 3)
@@ -5803,7 +5807,7 @@
   [(set (match_operand:XF 0 "register_operand" "")
 	(minus:XF (match_operand:XF 1 "register_operand" "")
 		  (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "")
 
 (define_expand "subtf3"
@@ -5920,12 +5924,26 @@
    (set_attr "length_immediate" "0")
    (set_attr "mode" "QI")])
 
+(define_insn "umulsi3"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(mult:SI (match_operand:SI 1 "register_operand" "%0")
+		 (match_operand:SI 2 "nonimmediate_operand" "rm")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))
+   (clobber (reg:CC 17))]
+  ""
+  "mul{l}\\t%2"
+  [(set_attr "type" "imul")
+   (set_attr "ppro_uops" "few")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "SI")])
+
+;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
 (define_insn "umulsidi3"
   [(set (match_operand:DI 0 "register_operand" "=A")
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
 		 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
    (clobber (reg:CC 17))]
-  ""
+  "!TARGET_64BIT"
   "mul{l}\\t%2"
   [(set_attr "type" "imul")
    (set_attr "ppro_uops" "few")
@@ -5937,7 +5955,7 @@
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
 		 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
    (clobber (reg:CC 17))]
-  ""
+  "!TARGET_64BIT"
   "imul{l}\\t%2"
   [(set_attr "type" "imul")
    (set_attr "length_immediate" "0")
@@ -5954,7 +5972,7 @@
 	    (const_int 32))))
    (clobber (match_scratch:SI 3 "=a"))
    (clobber (reg:CC 17))]
-  ""
+  "!TARGET_64BIT"
   "mul{l}\\t%2"
   [(set_attr "type" "imul")
    (set_attr "ppro_uops" "few")
@@ -5984,7 +6002,7 @@
   [(set (match_operand:XF 0 "register_operand" "")
 	(mult:XF (match_operand:XF 1 "register_operand" "")
 		 (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "")
 
 (define_expand "multf3"
@@ -6038,7 +6056,7 @@
   [(set (match_operand:XF 0 "register_operand" "")
 	(div:XF (match_operand:XF 1 "register_operand" "")
 		(match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "")
 
 (define_expand "divtf3"
@@ -7389,7 +7407,7 @@
   [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
 		   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
 	      (clobber (reg:CC 17))])]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
 
 (define_expand "negtf2"
@@ -7406,7 +7424,8 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
 	(neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && ix86_unary_operator_ok (NEG, XFmode, operands)"
+  "TARGET_80387 && !TARGET_64BIT
+   && ix86_unary_operator_ok (NEG, XFmode, operands)"
   "#")
 
 (define_split
@@ -7491,7 +7510,7 @@
 (define_insn "*negxf2_1"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(neg:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387 && reload_completed"
+  "TARGET_80387 && !TARGET_64BIT && reload_completed"
   "fchs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")
@@ -7501,7 +7520,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(neg:XF (float_extend:XF
 		  (match_operand:DF 1 "register_operand" "0"))))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "fchs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")
@@ -7511,7 +7530,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(neg:XF (float_extend:XF
 		  (match_operand:SF 1 "register_operand" "0"))))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "fchs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")
@@ -7643,7 +7662,7 @@
   [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
 		   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
 	      (clobber (reg:CC 17))])]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
 
 (define_expand "abstf2"
@@ -7660,7 +7679,8 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
 	(abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && ix86_unary_operator_ok (ABS, XFmode, operands)"
+  "TARGET_80387 && !TARGET_64BIT
+   && ix86_unary_operator_ok (ABS, XFmode, operands)"
   "#")
 
 (define_split
@@ -7736,7 +7756,7 @@
 (define_insn "*absxf2_1"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(abs:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387 && reload_completed"
+  "TARGET_80387 && !TARGET_64BIT && reload_completed"
   "fabs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "DF")])
@@ -7745,7 +7765,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(abs:XF (float_extend:XF
 	  (match_operand:DF 1 "register_operand" "0"))))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "fabs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")])
@@ -7754,7 +7774,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(abs:XF (float_extend:XF
 	  (match_operand:SF 1 "register_operand" "0"))))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "fabs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")])
@@ -8825,7 +8845,7 @@
 		     (match_operand:QI 2 "nonmemory_operand" "Jc")))
    (clobber (match_scratch:SI 3 "=&r"))
    (clobber (reg:CC 17))]
-  "TARGET_CMOVE"
+  "!TARGET_64BIT && TARGET_CMOVE"
   "#"
   [(set_attr "type" "multi")])
 
@@ -8834,7 +8854,7 @@
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
 		     (match_operand:QI 2 "nonmemory_operand" "Jc")))
    (clobber (reg:CC 17))]
-  ""
+  "!TARGET_64BIT"
   "#"
   [(set_attr "type" "multi")])
 
@@ -8844,7 +8864,7 @@
 		     (match_operand:QI 2 "nonmemory_operand" "")))
    (clobber (match_scratch:SI 3 ""))
    (clobber (reg:CC 17))]
-  "TARGET_CMOVE && reload_completed"
+  "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
   [(const_int 0)]
   "ix86_split_lshrdi (operands, operands[3]); DONE;")
 
@@ -8853,7 +8873,7 @@
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
 		     (match_operand:QI 2 "nonmemory_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed"
+  "!TARGET_64BIT && reload_completed"
   [(const_int 0)]
   "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
 
@@ -9987,7 +10007,7 @@
    (use (match_operand 2 "" ""))        ; max iterations
    (use (match_operand 3 "" ""))        ; loop level 
    (use (match_operand 4 "" ""))]       ; label
-  "TARGET_USE_LOOP"
+  "TARGET_USE_LOOP && !TARGET_64BIT"
   "                                 
 {
   /* Only use cloop on innermost loops.  */
@@ -10011,7 +10031,7 @@
 		 (const_int -1)))
    (clobber (match_scratch:SI 3 "=X,X,r"))
    (clobber (reg:CC 17))]
-  "TARGET_USE_LOOP"
+  "TARGET_USE_LOOP && !TARGET_64BIT"
   "*
 {
   if (which_alternative != 0)
@@ -10042,7 +10062,7 @@
 		 (const_int -1)))
    (clobber (match_scratch:SI 2 ""))
    (clobber (reg:CC 17))]
-  "TARGET_USE_LOOP
+  "TARGET_USE_LOOP && !TARGET_64BIT
    && reload_completed
    && REGNO (operands[1]) != 2"
   [(parallel [(set (reg:CCZ 17)
@@ -10065,7 +10085,7 @@
 		 (const_int -1)))
    (clobber (match_scratch:SI 3 ""))
    (clobber (reg:CC 17))]
-  "TARGET_USE_LOOP
+  "TARGET_USE_LOOP && !TARGET_64BIT
    && reload_completed
    && (! REG_P (operands[2])
        || ! rtx_equal_p (operands[1], operands[2]))"
@@ -10094,7 +10114,7 @@
 	      (set (reg:SI 7)
 		   (plus:SI (reg:SI 7)
 			    (match_operand:SI 3 "" "")))])]
-  ""
+  "!TARGET_64BIT"
   "
 {
   if (operands[3] == const0_rtx)
@@ -10110,6 +10130,8 @@
     current_function_uses_pic_offset_table = 1;
   if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
     XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
+  if (TARGET_64BIT)
+    abort();
 }")
 
 (define_insn "*call_pop_0"
@@ -10117,7 +10139,7 @@
 	 (match_operand:SI 1 "" ""))
    (set (reg:SI 7) (plus:SI (reg:SI 7)
 			    (match_operand:SI 2 "immediate_operand" "")))]
-  ""
+  "!TARGET_64BIT"
   "*
 {
   if (SIBLING_CALL_P (insn))
@@ -10132,7 +10154,7 @@
 	 (match_operand:SI 1 "" ""))
    (set (reg:SI 7) (plus:SI (reg:SI 7)
 			    (match_operand:SI 2 "immediate_operand" "i")))]
-  ""
+  "!TARGET_64BIT"
   "*
 {
   if (constant_call_address_operand (operands[0], Pmode))
@@ -10209,7 +10231,7 @@
 	      (set (reg:SI 7)
 		   (plus:SI (reg:SI 7)
 			    (match_operand:SI 4 "" "")))])]
-  ""
+  "!TARGET_64BIT"
   "
 {
   if (operands[4] == const0_rtx)
@@ -10375,7 +10397,7 @@
 (define_insn "prologue_get_pc"
   [(set (match_operand:SI 0 "register_operand" "=r")
     (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
-  ""
+  "!TARGET_64BIT"
   "*
 {
   if (GET_CODE (operands[1]) == LABEL_REF)
@@ -10403,7 +10425,7 @@
 (define_insn "leave"
   [(set (reg:SI 7) (reg:SI 6))
    (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))]
-  ""
+  "!TARGET_64BIT"
   "leave"
   [(set_attr "length_immediate" "0")
    (set_attr "length" "1")
@@ -10581,7 +10603,8 @@
 	(match_operator:XF 3 "binary_fp_operator"
 			[(match_operand:XF 1 "register_operand" "%0")
 			 (match_operand:XF 2 "register_operand" "f")]))]
-  "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
+  "TARGET_80387 && !TARGET_64BIT
+   && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (if_then_else (match_operand:XF 3 "mult_operator" "") 
@@ -10776,7 +10799,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 			[(match_operand:XF 1 "register_operand" "0,f")
 			 (match_operand:XF 2 "register_operand" "f,0")]))]
-  "TARGET_80387
+  "TARGET_80387 && !TARGET_64BIT
    && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
@@ -10810,7 +10833,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 	   [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
 	    (match_operand:XF 2 "register_operand" "0,0")]))]
-  "TARGET_80387 && TARGET_USE_FIOP"
+  "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -10846,7 +10869,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 	  [(match_operand:XF 1 "register_operand" "0,0")
 	   (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
-  "TARGET_80387 && TARGET_USE_FIOP"
+  "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -10882,7 +10905,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 	   [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
 	    (match_operand:XF 2 "register_operand" "0,f")]))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -10915,7 +10938,7 @@
 	  [(match_operand:XF 1 "register_operand" "0,f")
 	   (float_extend:XF
 	    (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -10948,7 +10971,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 	   [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
 	    (match_operand:XF 2 "register_operand" "0,f")]))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -10981,7 +11004,7 @@
 	  [(match_operand:XF 1 "register_operand" "0,f")
 	   (float_extend:XF
 	    (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
-  "TARGET_80387"
+  "TARGET_80387 && !TARGET_64BIT"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -11148,7 +11171,7 @@
 (define_insn "sqrtxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
    && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
   "fsqrt"
   [(set_attr "type" "fpspc")
@@ -11169,7 +11192,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(sqrt:XF (float_extend:XF
 		  (match_operand:DF 1 "register_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
@@ -11189,7 +11212,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(sqrt:XF (float_extend:XF
 		  (match_operand:SF 1 "register_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
@@ -11236,7 +11259,7 @@
 (define_insn "sinxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
    && flag_unsafe_math_optimizations"
   "fsin"
   [(set_attr "type" "fpspc")
@@ -11282,7 +11305,7 @@
 (define_insn "cosxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
    && flag_unsafe_math_optimizations"
   "fcos"
   [(set_attr "type" "fpspc")
@@ -12247,7 +12270,7 @@
 				[(reg 17) (const_int 0)])
 		      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
 		      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
-  "TARGET_CMOVE
+  "TARGET_CMOVE && !TARGET_64BIT
    && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
   "@
    fcmov%F1\\t{%2, %0|%0, %2}
@@ -12257,13 +12280,29 @@
   [(set_attr "type" "fcmov,fcmov,multi,multi")
    (set_attr "mode" "DF")])
 
+(define_insn "*movdfcc_1_rex64"
+  [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
+	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
+				[(reg 17) (const_int 0)])
+		      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
+		      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
+  "TARGET_CMOVE && TARGET_64BIT
+   && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
+  "@
+   fcmov%F1\\t{%2, %0|%0, %2}
+   fcmov%f1\\t{%3, %0|%0, %3}
+   cmov%C1\\t{%2, %0|%0, %2}
+   cmov%c1\\t{%3, %0|%0, %3}"
+  [(set_attr "type" "fcmov,fcmov,icmov,icmov")
+   (set_attr "mode" "DF")])
+
 (define_split
   [(set (match_operand:DF 0 "register_operand" "")
 	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
 				[(match_operand 4 "" "") (const_int 0)])
 		      (match_operand:DF 2 "nonimmediate_operand" "")
 		      (match_operand:DF 3 "nonimmediate_operand" "")))]
-  "!ANY_FP_REG_P (operands[0]) && reload_completed"
+  "!ANY_FP_REG_P (operands[0]) && reload_completed && !TARGET_64BIT"
   [(set (match_dup 2)
 	(if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
 		      (match_dup 5)
@@ -12281,7 +12320,7 @@
 	(if_then_else:XF (match_operand 1 "comparison_operator" "")
 			 (match_operand:XF 2 "register_operand" "")
 			 (match_operand:XF 3 "register_operand" "")))]
-  "TARGET_CMOVE"
+  "TARGET_CMOVE && !TARGET_64BIT"
   "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
 
 (define_expand "movtfcc"
@@ -12298,7 +12337,7 @@
 				[(reg 17) (const_int 0)])
 		      (match_operand:XF 2 "register_operand" "f,0")
 		      (match_operand:XF 3 "register_operand" "0,f")))]
-  "TARGET_CMOVE"
+  "TARGET_CMOVE && !TARGET_64BIT"
   "@
    fcmov%F1\\t{%2, %0|%0, %2}
    fcmov%f1\\t{%3, %0|%0, %3}"
@@ -13613,7 +13652,7 @@
 	      (match_operand:SI 2 "" "")))
    (set (reg:SI 7) (plus:SI (reg:SI 7)
 			    (match_operand:SI 3 "immediate_operand" "")))]
-  ""
+  "!TARGET_64BIT"
   "*
 {
   if (SIBLING_CALL_P (insn))
@@ -13629,7 +13668,7 @@
 	      (match_operand:SI 2 "" "")))
    (set (reg:SI 7) (plus:SI (reg:SI 7)
 			    (match_operand:SI 3 "immediate_operand" "i")))]
-  ""
+  "!TARGET_64BIT"
   "*
 {
   if (constant_call_address_operand (operands[1], QImode))