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| author | Alexandre Oliva <aoliva@redhat.com> | 2002-03-18 19:17:27 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@gcc.gnu.org> | 2002-03-18 19:17:27 +0000 |
| commit | 1bfbbbcf9d24810576bee99bb4551331ad412c12 (patch) | |
| tree | 6c066f2a51a6177bcb00b53068257b6fc1f84154 | |
| parent | c066429ee425b13780ac3e41bc6173687b46689e (diff) | |
| download | gcc-1bfbbbcf9d24810576bee99bb4551331ad412c12.zip gcc-1bfbbbcf9d24810576bee99bb4551331ad412c12.tar.gz gcc-1bfbbbcf9d24810576bee99bb4551331ad412c12.tar.bz2 | |
mips.md (andsi3): Force operand 1 to a register too.
* config/mips/mips.md (andsi3) [TARGET_MIPS16]: Force operand 1 to
a register too.
(anddi3, iorsi3): Likewise.
From-SVN: r50988
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 15 |
2 files changed, 16 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7bbb1b0..426e706 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2002-03-18 Alexandre Oliva <aoliva@redhat.com> + * config/mips/mips.md (andsi3) [TARGET_MIPS16]: Force operand 1 to + a register too. + (anddi3, iorsi3): Likewise. + * config/mips/mips.h (ENCODE_SECTION_INFO) [TARGET_MIPS16]: Don't use %gprel for symbols that are going to be placed in linkonce sections. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 60d560b..3f1cdd0 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3333,7 +3333,10 @@ move\\t%0,%z4\\n\\ " { if (TARGET_MIPS16) - operands[2] = force_reg (SImode, operands[2]); + { + operands[1] = force_reg (SImode, operands[1]); + operands[2] = force_reg (SImode, operands[2]); + } }") (define_insn "" @@ -3364,7 +3367,10 @@ move\\t%0,%z4\\n\\ " { if (TARGET_MIPS16) - operands[2] = force_reg (DImode, operands[2]); + { + operands[1] = force_reg (DImode, operands[1]); + operands[2] = force_reg (DImode, operands[2]); + } }") (define_insn "" @@ -3436,7 +3442,10 @@ move\\t%0,%z4\\n\\ " { if (TARGET_MIPS16) - operands[2] = force_reg (SImode, operands[2]); + { + operands[1] = force_reg (SImode, operands[1]); + operands[2] = force_reg (SImode, operands[2]); + } }") (define_insn "" |