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| author | Richard Sandiford <richard.sandiford@arm.com> | 2025-01-20 19:52:30 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2025-01-20 19:52:30 +0000 |
| commit | 1b8820421488d220a95f651b51175d618063c48c (patch) | |
| tree | 31d08fd0c739e5dbd79644cd3260df4b4c9ab463 | |
| parent | 9ab38952a2033d6d4a8e31c3c4d2ab1a25a406c6 (diff) | |
| download | gcc-1b8820421488d220a95f651b51175d618063c48c.zip gcc-1b8820421488d220a95f651b51175d618063c48c.tar.gz gcc-1b8820421488d220a95f651b51175d618063c48c.tar.bz2 | |
aarch64: Add missing simd requirements for INS [PR118531]
In g:b096a6ebe9d9f9fed4c105f6555f724eb32af95c I'd forgotten
to gate some uses of INS on TARGET_SIMD.
gcc/
PR target/118531
* config/aarch64/aarch64.md (*insv_reg<mode>_<SUBDI_BITS>)
(*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>)
(*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>): Add missing
simd requirements.
gcc/testsuite/
* gcc.target/aarch64/ins_bitfield_1a.c: New test.
* gcc.target/aarch64/ins_bitfield_3a.c: Likewise.
* gcc.target/aarch64/ins_bitfield_5a.c: Likewise.
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 9 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c | 8 |
4 files changed, 30 insertions, 3 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 44f5b7a..1b67ccc 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -6361,7 +6361,8 @@ return "ins\t%0.<bits_etype>[%1], %2.<bits_etype>[0]"; return "ins\t%0.<bits_etype>[%1], %w2"; } - [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")] + [(set_attr "type" "bfm,neon_ins_q,neon_ins_q") + (set_attr "arch" "*,simd,simd")] ) (define_insn "*insv_reg<mode>" @@ -6394,7 +6395,8 @@ operands[2] = lowpart_subreg (<GPI:MODE>mode, operands[2], <ALLX:MODE>mode); } - [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")] + [(set_attr "type" "bfm,neon_ins_q,neon_ins_q") + (set_attr "arch" "*,simd,simd")] ) (define_insn "*aarch64_bfi<GPI:mode><ALLX:mode>4" @@ -6426,7 +6428,8 @@ { operands[2] = lowpart_subreg (DImode, operands[3], <ALLX:MODE>mode); } - [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")] + [(set_attr "type" "bfm,neon_ins_q,neon_ins_q") + (set_attr "arch" "*,simd,simd")] ) ;; Match a bfi instruction where the shift of OP3 means that we are diff --git a/gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c new file mode 100644 index 0000000..028d4aa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 --save-temps" } */ + +#pragma GCC target "+nosimd" + +#include "ins_bitfield_1.c" + +/* { dg-final { scan-assembler-not {\tins\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c new file mode 100644 index 0000000..1c15366 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 --save-temps" } */ + +#pragma GCC target "+nosimd" + +#include "ins_bitfield_3.c" + +/* { dg-final { scan-assembler-not {\tins\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c new file mode 100644 index 0000000..f6bdde9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c @@ -0,0 +1,8 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 --save-temps" } */ + +#pragma GCC target "+nosimd" + +#include "ins_bitfield_5.c" + +/* { dg-final { scan-assembler-not {\tins\t} } } */ |