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| author | Vineet Gupta <vineetg@rivosinc.com> | 2024-10-24 15:15:40 -0700 |
|---|---|---|
| committer | Vineet Gupta <vineetg@rivosinc.com> | 2024-10-31 09:52:45 -0700 |
| commit | 1905b59fdc58ce67e508b99dff105afebaaa9bb1 (patch) | |
| tree | 786688adc0eabc16f025773c79192f8695783aa4 | |
| parent | da9772be0ceee9b9a3f6f8ff20df939ce8063660 (diff) | |
| download | gcc-1905b59fdc58ce67e508b99dff105afebaaa9bb1.zip gcc-1905b59fdc58ce67e508b99dff105afebaaa9bb1.tar.gz gcc-1905b59fdc58ce67e508b99dff105afebaaa9bb1.tar.bz2 | |
RISC-V: fix const interleaved stepped vector with a scalar pattern
When bisecting for ICE in PR/117353, commit 771256bcb9dd ("RISC-V: Emit costs for
bool and stepped const vectors") uncovered yet another latent issue (first noted [1])
[1] https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1625
This patch fixes some of the fortran regressions from that report.
Fixes 71a5ac6703d1 ("RISC-V: Support interleave vector with different step sequence")
rv64imafdcv_zvl256b_zba_zbb_zbs_zicond/lp64d/medlow
| # of unexpected case / # of unique unexpected case
| gcc | g++ | gfortran |
| 392 / 108 | 7 / 3 | 91 / 24 |
| 392 / 108 | 7 / 3 | 67 / 12 |
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Use IOR op.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/slp-interleave-5.c: New test.
Tested-by: Edwin Lu <ewlu@rivosinc.com> # Pre-commit CU #2503
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
| -rw-r--r-- | gcc/config/riscv/riscv-v.cc | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c | 35 |
2 files changed, 38 insertions, 3 deletions
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 209b7ee..5e728f0 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1501,9 +1501,9 @@ expand_const_vector (rtx target, rtx src) gen_int_mode (builder.inner_bits_size (), new_smode), NULL_RTX, false, OPTAB_DIRECT); rtx tmp2 = gen_reg_rtx (new_mode); - rtx and_ops[] = {tmp2, tmp1, scalar}; - emit_vlmax_insn (code_for_pred_scalar (AND, new_mode), - BINARY_OP, and_ops); + rtx ior_ops[] = {tmp2, tmp1, scalar}; + emit_vlmax_insn (code_for_pred_scalar (IOR, new_mode), + BINARY_OP, ior_ops); emit_move_insn (result, gen_lowpart (mode, tmp2)); } else diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c new file mode 100644 index 0000000..32cfe8a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -O3 -fdump-tree-optimized-details" } */ + +struct S { int a, b; } s[8]; + +void +foo () +{ + int i; + for (i = 0; i < 8; i++) + { + s[i].b = 1; + s[i].a = i+1; + } +} + +/* { dg-final { scan-tree-dump-times "\{ 1, 1, 2, 1, 3, 1, 4, 1 \}" 1 "optimized" } } */ +/* { dg-final { scan-assembler {vid\.v} } } */ +/* { dg-final { scan-assembler {vadd\.v} } } */ +/* { dg-final { scan-assembler {vor\.v} } } */ + +void +foo2 () +{ + int i; + for (i = 0; i < 8; i++) + { + s[i].b = 0; + s[i].a = i+1; + } +} + +/* { dg-final { scan-tree-dump-times "\{ 1, 0, 2, 0, 3, 0, 4, 0 \}" 1 "optimized" } } */ +/* { dg-final { scan-assembler {vid\.v} } } */ +/* { dg-final { scan-assembler {vadd\.v} } } */ |