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| author | Richard Earnshaw <rearnsha@arm.com> | 2018-08-09 13:39:17 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2018-08-09 13:39:17 +0000 |
| commit | 16621f0de36074287eca820cd34de79ab8ee3486 (patch) | |
| tree | 22a225d6fa78251c77914063f23d64ce3e255168 | |
| parent | 40c27f7d974e45f49261cb6997df8fae7c88b80f (diff) | |
| download | gcc-16621f0de36074287eca820cd34de79ab8ee3486.zip gcc-16621f0de36074287eca820cd34de79ab8ee3486.tar.gz gcc-16621f0de36074287eca820cd34de79ab8ee3486.tar.bz2 | |
aarch64 - PR target/86887 Fix missing register constraints in carryin patterns
Some of the carryin insn patterns are missing a register constraint.
That means that the register allocator can pick practically anything
to hold that value, including memory locations, or registers of the
wrong class.
PR target/86887
* config/aarch64/aarch64.md (add<mode>3_carryinC_zero): Add missing
register constraint to operand 0.
(add<mode>3_carryinC): Likewise.
(add<mode>3_carryinV_zero, add<mode>3_carryinV): Likewise.
From-SVN: r263446
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 8 |
2 files changed, 12 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9ff7c21..9d5a23f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2018-08-09 Richard Earnshaw <rearnsha@arm.com> + + PR target/86887 + * config/aarch64/aarch64.md (add<mode>3_carryinC_zero): Add missing + register constraint to operand 0. + (add<mode>3_carryinC): Likewise. + (add<mode>3_carryinV_zero, add<mode>3_carryinV): Likewise. + 2018-08-09 Martin Liska <mliska@suse.cz> PR c/86895 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 8035856..22d20ea 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2451,7 +2451,7 @@ (plus:GPI (match_operand:GPI 3 "aarch64_carry_operation" "") (match_dup 1))))) - (set (match_operand:GPI 0 "register_operand") + (set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (match_dup 3) (match_dup 1)))] "" "adcs\\t%<w>0, %<w>1, <w>zr" @@ -2472,7 +2472,7 @@ (match_operand:GPI 4 "aarch64_carry_operation" "") (match_dup 1)) (match_dup 2))))) - (set (match_operand:GPI 0 "register_operand") + (set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (plus:GPI (match_dup 4) (match_dup 1)) (match_dup 2)))] @@ -2517,7 +2517,7 @@ (plus:GPI (match_operand:GPI 3 "aarch64_carry_operation" "") (match_dup 1))))) - (set (match_operand:GPI 0 "register_operand") + (set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (match_dup 3) (match_dup 1)))] "" "adcs\\t%<w>0, %<w>1, <w>zr" @@ -2538,7 +2538,7 @@ (match_operand:GPI 4 "aarch64_carry_operation" "") (match_dup 1)) (match_dup 2))))) - (set (match_operand:GPI 0 "register_operand") + (set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (plus:GPI (match_dup 4) (match_dup 1)) (match_dup 2)))] |