2007-xx-xx Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> Thiemo...

gcc/
2007-xx-xx  Nigel Stephens  <nigel@mips.com>
	    David Ung  <davidu@mips.com>
	    Thiemo Seufer  <ths@mips.com>
	    Chris Dearman  <chris@mips.com>
	    Richard Sandiford  <richard@codesourcery.com>

	* config.gcc (mips*-sde-elf*): New stanza.
	(mipsisa32-*-elf*, mipsisa32el-*-elf*, mipsisa32r2-*-elf*)
	(mipsisa32r2el-*-elf*, mipsisa64-*-elf*, mipsisa64el-*-elf*)
	(mipsisa64sb1-*-elf*, mipsisa64sb1el-*-elf*, mips-*-elf*)
	(mipsel-*-elf*, mips64-*-elf*, mips64el-*-elf*, mips64orion-*-elf*)
	(mips64orionel-*-elf*, mips*-*-rtems*, mips-wrs-windiss)
	(mipstx39-*-elf*, mipstx39el-*-elf*): Add mips/t-libgcc-mips16
	to tmake_file.
	* config/mips/sde.h: New file.
	* config/mips/t-libgcc-mips16: Likewise.
	* config/mips/t-sde: Likewise.
	* config/mips/linux.h (TARGET_OS_CPP_BUILTINS): Remove settings
	of _ABIN32, _ABI64, _ABIO32, _MIPS_SIM, _MIPS_SZLONG, _MIPS_SZPTR,
	_MIPS_FPSET and _MIPS_SZINT.
	* config/mips/iris.h (TARGET_OS_CPP_BUILTINS): Likewise.
	* config/mips/elfoabi.h (DRIVER_SELF_SPECS): Remove separate
	insertion of a default -mips option.  Use MIPS_32BIT_OPTION_SPEC.
	* config/mips/t-isa3264 (LIB1ASMSRC, LIB1ASMFUNCS): Delete.
	* config/mips/t-r3900 (LIB1ASMSRC, LIB1ASMFUNCS): Likewise.
	* config/mips/t-elf (LIB1ASMSRC, LIB1ASMFUNCS): Likewise.
	* config/mips/mips.h (TARGET_CPU_CPP_BUITINS): Define _ABIO32,
	_ABIN32, _ABI64, _ABIO64, _MIPS_SIM, _MIPS_SZINT, _MIPS_SZLONG,
	_MIPS_SZPTR and _MIPS_FPSET.
	(MIPS_ISA_LEVEL_SPEC): Inject the default -mips option if no
	architecture is specified.
	(MIPS_32BIT_OPTION_SPEC): New macro.

Co-Authored-By: Chris Dearman <chris@mips.com>
Co-Authored-By: David Ung <davidu@mips.com>
Co-Authored-By: Richard Sandiford <richard@codesourcery.com>
Co-Authored-By: Thiemo Seufer <ths@mips.com>

From-SVN: r127113

12 files changed, 462 insertions, 294 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ede2584..9d61037 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,36 @@
+2007-08-01  Nigel Stephens  <nigel@mips.com>
+	    David Ung  <davidu@mips.com>
+	    Thiemo Seufer  <ths@mips.com>
+	    Chris Dearman  <chris@mips.com>
+	    Richard Sandiford  <richard@codesourcery.com>
+
+	* config.gcc (mips*-sde-elf*): New stanza.
+	(mipsisa32-*-elf*, mipsisa32el-*-elf*, mipsisa32r2-*-elf*)
+	(mipsisa32r2el-*-elf*, mipsisa64-*-elf*, mipsisa64el-*-elf*)
+	(mipsisa64sb1-*-elf*, mipsisa64sb1el-*-elf*, mips-*-elf*)
+	(mipsel-*-elf*, mips64-*-elf*, mips64el-*-elf*, mips64orion-*-elf*)
+	(mips64orionel-*-elf*, mips*-*-rtems*, mips-wrs-windiss)
+	(mipstx39-*-elf*, mipstx39el-*-elf*): Add mips/t-libgcc-mips16
+	to tmake_file.
+	* config/mips/sde.h: New file.
+	* config/mips/t-libgcc-mips16: Likewise.
+	* config/mips/t-sde: Likewise.
+	* config/mips/linux.h (TARGET_OS_CPP_BUILTINS): Remove settings
+	of _ABIN32, _ABI64, _ABIO32, _MIPS_SIM, _MIPS_SZLONG, _MIPS_SZPTR,
+	_MIPS_FPSET and _MIPS_SZINT.
+	* config/mips/iris.h (TARGET_OS_CPP_BUILTINS): Likewise.
+	* config/mips/elfoabi.h (DRIVER_SELF_SPECS): Remove separate
+	insertion of a default -mips option.  Use MIPS_32BIT_OPTION_SPEC.
+	* config/mips/t-isa3264 (LIB1ASMSRC, LIB1ASMFUNCS): Delete.
+	* config/mips/t-r3900 (LIB1ASMSRC, LIB1ASMFUNCS): Likewise.
+	* config/mips/t-elf (LIB1ASMSRC, LIB1ASMFUNCS): Likewise.
+	* config/mips/mips.h (TARGET_CPU_CPP_BUITINS): Define _ABIO32,
+	_ABIN32, _ABI64, _ABIO64, _MIPS_SIM, _MIPS_SZINT, _MIPS_SZLONG,
+	_MIPS_SZPTR and _MIPS_FPSET.
+	(MIPS_ISA_LEVEL_SPEC): Inject the default -mips option if no
+	architecture is specified.
+	(MIPS_32BIT_OPTION_SPEC): New macro.
+
 2007-07-31  Dan Hipschman  <dsh@google.com>
 
 	* gcc.c (end_going_arg): New function.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index fbd2671..b7bc072 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -1678,11 +1678,26 @@ mips*-*-openbsd*)
 	*)  tm_defines="${tm_defines} TARGET_ENDIAN_DEFAULT=MASK_BIG_ENDIAN";;
         esac
 	;;
+mips*-sde-elf*)
+	tm_file="elfos.h ${tm_file} mips/elf.h mips/sde.h"
+	tmake_file="mips/t-sde mips/t-libgcc-mips16"
+	case ${target} in
+	  mipsisa32r2*)
+	    tm_defines="MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32"
+	    ;;
+	  mipsisa32*)
+	    tm_defines="MIPS_ISA_DEFAULT=32 MIPS_ABI_DEFAULT=ABI_32"
+	    ;;
+	  mipsisa64*)
+	    tm_defines="MIPS_ISA_DEFAULT=64 MIPS_ABI_DEFAULT=ABI_N32"
+	    ;;
+	esac
+	;;
 mipsisa32-*-elf* | mipsisa32el-*-elf* | \
 mipsisa32r2-*-elf* | mipsisa32r2el-*-elf* | \
 mipsisa64-*-elf* | mipsisa64el-*-elf*)
 	tm_file="elfos.h ${tm_file} mips/elf.h"
-	tmake_file=mips/t-isa3264
+	tmake_file="mips/t-isa3264 mips/t-libgcc-mips16"
 	case ${target} in
 	  mipsisa32r2*)
 	    tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33"
@@ -1717,19 +1732,19 @@ mipsisa64sr71k-*-elf*)
         ;;
 mipsisa64sb1-*-elf* | mipsisa64sb1el-*-elf*)
 	tm_file="elfos.h ${tm_file} mips/elf.h"
-	tmake_file="mips/t-elf mips/t-sb1"
+	tmake_file="mips/t-elf mips/t-libgcc-mips16 mips/t-sb1"
 	target_cpu_default="MASK_64BIT|MASK_FLOAT64"
 	tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64 MIPS_CPU_STRING_DEFAULT=\\\"sb1\\\" MIPS_ABI_DEFAULT=ABI_O64"
 	use_fixproto=yes
 	;;
 mips-*-elf* | mipsel-*-elf*)
 	tm_file="elfos.h ${tm_file} mips/elf.h"
-	tmake_file=mips/t-elf
+	tmake_file="mips/t-elf mips/t-libgcc-mips16"
 	use_fixproto=yes
 	;;
 mips64-*-elf* | mips64el-*-elf*)
 	tm_file="elfos.h ${tm_file} mips/elf.h"
-	tmake_file=mips/t-elf
+	tmake_file="mips/t-elf mips/t-libgcc-mips16"
 	target_cpu_default="MASK_64BIT|MASK_FLOAT64"
 	tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64"
 	use_fixproto=yes
@@ -1741,14 +1756,14 @@ mips64vr-*-elf* | mips64vrel-*-elf*)
         ;;
 mips64orion-*-elf* | mips64orionel-*-elf*)
 	tm_file="elfos.h ${tm_file} mips/elforion.h mips/elf.h"
-	tmake_file=mips/t-elf
+	tmake_file="mips/t-elf mips/t-libgcc-mips16"
 	target_cpu_default="MASK_64BIT|MASK_FLOAT64"
 	tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64"
 	use_fixproto=yes
 	;;
 mips*-*-rtems*)
 	tm_file="elfos.h ${tm_file} mips/elf.h mips/rtems.h rtems.h"
-	tmake_file="mips/t-elf t-rtems mips/t-rtems"
+	tmake_file="mips/t-elf mips/t-libgcc-mips16 t-rtems mips/t-rtems"
 	;;
 mips-wrs-vxworks)
 	tm_file="elfos.h ${tm_file} svr4.h mips/elf.h vx-common.h vxworks.h mips/vxworks.h"
@@ -1757,12 +1772,12 @@ mips-wrs-vxworks)
 mips-wrs-windiss)	# Instruction-level simulator for VxWorks.
 	xm_defines=POSIX
 	tm_file="elfos.h mips/mips.h svr4.h mips/elf.h windiss.h mips/windiss.h"
-	tmake_file="${tmake_file} mips/t-elf"
+	tmake_file="${tmake_file} mips/t-elf mips/t-libgcc-mips16"
 	thread_file=
 	;;
 mipstx39-*-elf* | mipstx39el-*-elf*)
 	tm_file="elfos.h ${tm_file} mips/r3900.h mips/elf.h"
-	tmake_file=mips/t-r3900
+	tmake_file="mips/t-r3900 mips/t-libgcc-mips16"
 	use_fixproto=yes
 	;;
 mmix-knuth-mmixware)
diff --git a/gcc/config/mips/elfoabi.h b/gcc/config/mips/elfoabi.h
index a6cffe1..69930e2 100644
--- a/gcc/config/mips/elfoabi.h
+++ b/gcc/config/mips/elfoabi.h
@@ -21,19 +21,14 @@ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
 Boston, MA 02110-1301, USA.  */
 
 #define DRIVER_SELF_SPECS						\
-  /* Infer a -mips option from a -march option.  This makes		\
-     -march pick the right multilib, and also makes the later		\
-     specs easier to write.  */						\
+  /* Make sure a -mips option is present.  This helps us to pick	\
+     the right multilib, and also makes the later specs easier		\
+     to write.  */							\
   MIPS_ISA_LEVEL_SPEC,							\
 									\
-  /* If no architecture option is specified, force the default to	\
-     be listed explicitly.  This too makes later specs easier to	\
-     write.  */							       	\
-  "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: -" MULTILIB_ISA_DEFAULT "}",	\
-									\
   /* If no ABI option is specified, infer one from the ISA level	\
      or -mgp setting.  */						\
-  "%{!mabi=*: %{mips1|mips2|mips32*|mgp32: -mabi=32;: -mabi=o64}}",	\
+  "%{!mabi=*: %{" MIPS_32BIT_OPTION_SPEC ": -mabi=32;: -mabi=o64}}"	\
 									\
   /* Remove a redundant -mfp64 for -mabi=o64; we want the !mfp64	\
      multilibs.  There's no need to check whether the architecture	\
diff --git a/gcc/config/mips/iris.h b/gcc/config/mips/iris.h
index 58775e7..c71df49 100644
--- a/gcc/config/mips/iris.h
+++ b/gcc/config/mips/iris.h
@@ -100,39 +100,9 @@ Boston, MA 02110-1301, USA.  */
       builtin_assert ("system=svr4");				\
       builtin_assert ("machine=sgi");				\
 								\
-      if (mips_abi == ABI_32)					\
-	{							\
-	  builtin_define ("_ABIO32=1");				\
-	  builtin_define ("_MIPS_SIM=_ABIO32");			\
-	  builtin_define ("_MIPS_SZINT=32");			\
-	  builtin_define ("_MIPS_SZLONG=32");			\
-	  builtin_define ("_MIPS_SZPTR=32");			\
-	}							\
-      else if (mips_abi == ABI_64)				\
-	{							\
-	  builtin_define ("_ABI64=3");				\
-	  builtin_define ("_MIPS_SIM=_ABI64");			\
-	  builtin_define ("_MIPS_SZINT=32");			\
-	  builtin_define ("_MIPS_SZLONG=64");			\
-	  builtin_define ("_MIPS_SZPTR=64");			\
-	}							\
-      else							\
-	{							\
-	  builtin_define ("_ABIN32=2");				\
-	  builtin_define ("_MIPS_SIM=_ABIN32");			\
-	  builtin_define ("_MIPS_SZINT=32");			\
-	  builtin_define ("_MIPS_SZLONG=32");			\
-	  builtin_define ("_MIPS_SZPTR=32");			\
-        }							\
-								\
       if (!ISA_MIPS1 && !ISA_MIPS2)				\
 	builtin_define ("_COMPILER_VERSION=601");		\
 								\
-      if (!TARGET_FLOAT64)					\
-	builtin_define ("_MIPS_FPSET=16");			\
-      else							\
-	builtin_define ("_MIPS_FPSET=32");			\
-								\
       /* We must always define _LONGLONG, even when -ansi is	\
 	 used, because IRIX 5 system header files require it.	\
 	 This is OK, because gcc never warns when long long	\
diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
index e5d908e..024b5c5 100644
--- a/gcc/config/mips/linux.h
+++ b/gcc/config/mips/linux.h
@@ -59,34 +59,6 @@ Boston, MA 02110-1301, USA.  */
     /* The GNU C++ standard library requires this.  */		\
     if (c_dialect_cxx ())					\
       builtin_define ("_GNU_SOURCE");				\
-    								\
-    if (mips_abi == ABI_N32)					\
-      {								\
-        builtin_define ("_ABIN32=2");				\
-        builtin_define ("_MIPS_SIM=_ABIN32");			\
-        builtin_define ("_MIPS_SZLONG=32");			\
-        builtin_define ("_MIPS_SZPTR=32");			\
-      }								\
-    else if (mips_abi == ABI_64)				\
-      {								\
-        builtin_define ("_ABI64=3");				\
-        builtin_define ("_MIPS_SIM=_ABI64");			\
-        builtin_define ("_MIPS_SZLONG=64");			\
-        builtin_define ("_MIPS_SZPTR=64");			\
-      }								\
-    else							\
-      {								\
-	builtin_define ("_ABIO32=1");				\
-	builtin_define ("_MIPS_SIM=_ABIO32");			\
-        builtin_define ("_MIPS_SZLONG=32");			\
-        builtin_define ("_MIPS_SZPTR=32");			\
-      }								\
-    if (TARGET_FLOAT64)						\
-      builtin_define ("_MIPS_FPSET=32");			\
-    else							\
-      builtin_define ("_MIPS_FPSET=16");			\
-    								\
-    builtin_define ("_MIPS_SZINT=32");				\
   } while (0)
 
 #undef SUBTARGET_CPP_SPEC
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 181f03a..fa1a138 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -328,163 +328,192 @@ extern const struct mips_rtx_cost_data *mips_cost;
   while (0)
 
 /* Target CPU builtins.  */
-#define TARGET_CPU_CPP_BUILTINS()				\
-  do								\
-    {								\
-      /* Everyone but IRIX defines this to mips.  */            \
-      if (!TARGET_IRIX)                                         \
-        builtin_assert ("machine=mips");                        \
-                                                                \
-      builtin_assert ("cpu=mips");				\
-      builtin_define ("__mips__");     				\
-      builtin_define ("_mips");					\
-								\
-      /* We do this here because __mips is defined below	\
-	 and so we can't use builtin_define_std.  */		\
-      if (!flag_iso)						\
-	builtin_define ("mips");				\
-								\
-      if (TARGET_64BIT)						\
-	builtin_define ("__mips64");				\
-								\
-      if (!TARGET_IRIX)						\
-	{							\
-	  /* Treat _R3000 and _R4000 like register-size		\
-	     defines, which is how they've historically		\
-	     been used.  */					\
-	  if (TARGET_64BIT)					\
-	    {							\
-	      builtin_define_std ("R4000");			\
-	      builtin_define ("_R4000");			\
-	    }							\
-	  else							\
-	    {							\
-	      builtin_define_std ("R3000");			\
-	      builtin_define ("_R3000");			\
-	    }							\
-	}							\
-      if (TARGET_FLOAT64)					\
-	builtin_define ("__mips_fpr=64");			\
-      else							\
-	builtin_define ("__mips_fpr=32");			\
-								\
-      if (TARGET_MIPS16)					\
-	builtin_define ("__mips16");				\
-								\
-      if (TARGET_MIPS3D)					\
-	builtin_define ("__mips3d");				\
-                                                                \
-      if (TARGET_SMARTMIPS)					\
-	builtin_define ("__mips_smartmips");			\
-								\
-      if (TARGET_DSP)						\
-	{							\
-	  builtin_define ("__mips_dsp");			\
-	  if (TARGET_DSPR2)					\
-	    {							\
-	      builtin_define ("__mips_dspr2");			\
-	      builtin_define ("__mips_dsp_rev=2");		\
-	    }							\
-	  else							\
-	    builtin_define ("__mips_dsp_rev=1");		\
-	}							\
-								\
-      MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info);	\
-      MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info);	\
-								\
-      if (ISA_MIPS1)						\
-	{							\
-	  builtin_define ("__mips=1");				\
-	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1");		\
-	}							\
-      else if (ISA_MIPS2)					\
-	{							\
-	  builtin_define ("__mips=2");				\
-	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2");		\
-	}							\
-      else if (ISA_MIPS3)					\
-	{							\
-	  builtin_define ("__mips=3");				\
-	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3");		\
-	}							\
-      else if (ISA_MIPS4)					\
-	{							\
-	  builtin_define ("__mips=4");				\
-	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4");		\
-	}							\
-      else if (ISA_MIPS32)					\
-	{							\
-	  builtin_define ("__mips=32");				\
-	  builtin_define ("__mips_isa_rev=1");			\
-	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");	\
-	}							\
-      else if (ISA_MIPS32R2)					\
-	{							\
-	  builtin_define ("__mips=32");				\
-	  builtin_define ("__mips_isa_rev=2");			\
-	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");	\
-	}							\
-      else if (ISA_MIPS64)					\
-	{							\
-	  builtin_define ("__mips=64");				\
-	  builtin_define ("__mips_isa_rev=1");			\
-	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");	\
-	}							\
-								\
-      /* These defines reflect the ABI in use, not whether the  \
-	 FPU is directly accessible.  */			\
-      if (TARGET_HARD_FLOAT_ABI)				\
-	builtin_define ("__mips_hard_float");			\
-      else							\
-	builtin_define ("__mips_soft_float");			\
-								\
-      if (TARGET_SINGLE_FLOAT)					\
-	builtin_define ("__mips_single_float");			\
-								\
-      if (TARGET_PAIRED_SINGLE_FLOAT)				\
-	builtin_define ("__mips_paired_single_float");		\
-								\
-      if (TARGET_BIG_ENDIAN)					\
-	{							\
-	  builtin_define_std ("MIPSEB");			\
-	  builtin_define ("_MIPSEB");				\
-	}							\
-      else							\
-	{							\
-	  builtin_define_std ("MIPSEL");			\
-	  builtin_define ("_MIPSEL");				\
-	}							\
-								\
-        /* Macros dependent on the C dialect.  */		\
-      if (preprocessing_asm_p ())				\
-	{							\
-          builtin_define_std ("LANGUAGE_ASSEMBLY");		\
-	  builtin_define ("_LANGUAGE_ASSEMBLY");		\
-	}							\
-      else if (c_dialect_cxx ())				\
-        {							\
-	  builtin_define ("_LANGUAGE_C_PLUS_PLUS");		\
-          builtin_define ("__LANGUAGE_C_PLUS_PLUS");		\
-          builtin_define ("__LANGUAGE_C_PLUS_PLUS__");		\
-        }							\
-      else							\
-	{							\
-          builtin_define_std ("LANGUAGE_C");			\
-	  builtin_define ("_LANGUAGE_C");			\
-	}							\
-      if (c_dialect_objc ())					\
-        {							\
-	  builtin_define ("_LANGUAGE_OBJECTIVE_C");		\
-          builtin_define ("__LANGUAGE_OBJECTIVE_C");		\
-	  /* Bizarre, but needed at least for Irix.  */		\
-	  builtin_define_std ("LANGUAGE_C");			\
-	  builtin_define ("_LANGUAGE_C");			\
-        }							\
-								\
-      if (mips_abi == ABI_EABI)					\
-	builtin_define ("__mips_eabi");				\
-								\
-} while (0)
+#define TARGET_CPU_CPP_BUILTINS()					\
+  do									\
+    {									\
+      /* Everyone but IRIX defines this to mips.  */            	\
+      if (!TARGET_IRIX)                                         	\
+	builtin_assert ("machine=mips");                        	\
+									\
+      builtin_assert ("cpu=mips");					\
+      builtin_define ("__mips__");     					\
+      builtin_define ("_mips");						\
+									\
+      /* We do this here because __mips is defined below		\
+	 and so we can't use builtin_define_std.  */			\
+      if (!flag_iso)							\
+	builtin_define ("mips");					\
+									\
+      if (TARGET_64BIT)							\
+	builtin_define ("__mips64");					\
+									\
+      if (!TARGET_IRIX)							\
+	{								\
+	  /* Treat _R3000 and _R4000 like register-size			\
+	     defines, which is how they've historically			\
+	     been used.  */						\
+	  if (TARGET_64BIT)						\
+	    {								\
+	      builtin_define_std ("R4000");				\
+	      builtin_define ("_R4000");				\
+	    }								\
+	  else								\
+	    {								\
+	      builtin_define_std ("R3000");				\
+	      builtin_define ("_R3000");				\
+	    }								\
+	}								\
+      if (TARGET_FLOAT64)						\
+	builtin_define ("__mips_fpr=64");				\
+      else								\
+	builtin_define ("__mips_fpr=32");				\
+									\
+      if (TARGET_MIPS16)						\
+	builtin_define ("__mips16");					\
+									\
+      if (TARGET_MIPS3D)						\
+	builtin_define ("__mips3d");					\
+									\
+      if (TARGET_SMARTMIPS)						\
+	builtin_define ("__mips_smartmips");				\
+									\
+      if (TARGET_DSP)							\
+	{								\
+	  builtin_define ("__mips_dsp");				\
+	  if (TARGET_DSPR2)						\
+	    {								\
+	      builtin_define ("__mips_dspr2");				\
+	      builtin_define ("__mips_dsp_rev=2");			\
+	    }								\
+	  else								\
+	    builtin_define ("__mips_dsp_rev=1");			\
+	}								\
+									\
+      MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info);		\
+      MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info);		\
+									\
+      if (ISA_MIPS1)							\
+	{								\
+	  builtin_define ("__mips=1");					\
+	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1");			\
+	}								\
+      else if (ISA_MIPS2)						\
+	{								\
+	  builtin_define ("__mips=2");					\
+	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2");			\
+	}								\
+      else if (ISA_MIPS3)						\
+	{								\
+	  builtin_define ("__mips=3");					\
+	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3");			\
+	}								\
+      else if (ISA_MIPS4)						\
+	{								\
+	  builtin_define ("__mips=4");					\
+	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4");			\
+	}								\
+      else if (ISA_MIPS32)						\
+	{								\
+	  builtin_define ("__mips=32");					\
+	  builtin_define ("__mips_isa_rev=1");				\
+	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");		\
+	}								\
+      else if (ISA_MIPS32R2)						\
+	{								\
+	  builtin_define ("__mips=32");					\
+	  builtin_define ("__mips_isa_rev=2");				\
+	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32");		\
+	}								\
+      else if (ISA_MIPS64)						\
+	{								\
+	  builtin_define ("__mips=64");					\
+	  builtin_define ("__mips_isa_rev=1");				\
+	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");		\
+	}								\
+									\
+      switch (mips_abi)							\
+	{								\
+	case ABI_32:							\
+	  builtin_define ("_ABIO32=1");					\
+	  builtin_define ("_MIPS_SIM=_ABIO32");				\
+	  break;							\
+									\
+	case ABI_N32:							\
+	  builtin_define ("_ABIN32=2");					\
+	  builtin_define ("_MIPS_SIM=_ABIN32");				\
+	  break;							\
+									\
+	case ABI_64:							\
+	  builtin_define ("_ABI64=3");					\
+	  builtin_define ("_MIPS_SIM=_ABI64");				\
+	  break;							\
+									\
+	case ABI_O64:							\
+	  builtin_define ("_ABIO64=4");					\
+	  builtin_define ("_MIPS_SIM=_ABIO64");				\
+	  break;							\
+	}								\
+									\
+      builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE);	\
+      builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE);	\
+      builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE);	\
+      builtin_define_with_int_value ("_MIPS_FPSET",			\
+				     32 / MAX_FPRS_PER_FMT);		\
+									\
+      /* These defines reflect the ABI in use, not whether the  	\
+	 FPU is directly accessible.  */				\
+      if (TARGET_HARD_FLOAT_ABI)					\
+	builtin_define ("__mips_hard_float");				\
+      else								\
+	builtin_define ("__mips_soft_float");				\
+									\
+      if (TARGET_SINGLE_FLOAT)						\
+	builtin_define ("__mips_single_float");				\
+									\
+      if (TARGET_PAIRED_SINGLE_FLOAT)					\
+	builtin_define ("__mips_paired_single_float");			\
+									\
+      if (TARGET_BIG_ENDIAN)						\
+	{								\
+	  builtin_define_std ("MIPSEB");				\
+	  builtin_define ("_MIPSEB");					\
+	}								\
+      else								\
+	{								\
+	  builtin_define_std ("MIPSEL");				\
+	  builtin_define ("_MIPSEL");					\
+	}								\
+									\
+      /* Macros dependent on the C dialect.  */				\
+      if (preprocessing_asm_p ())					\
+	{								\
+	  builtin_define_std ("LANGUAGE_ASSEMBLY");			\
+	  builtin_define ("_LANGUAGE_ASSEMBLY");			\
+	}								\
+      else if (c_dialect_cxx ())					\
+	{								\
+	  builtin_define ("_LANGUAGE_C_PLUS_PLUS");			\
+	  builtin_define ("__LANGUAGE_C_PLUS_PLUS");			\
+	  builtin_define ("__LANGUAGE_C_PLUS_PLUS__");			\
+	}								\
+      else								\
+	{								\
+	  builtin_define_std ("LANGUAGE_C");				\
+	  builtin_define ("_LANGUAGE_C");				\
+	}								\
+      if (c_dialect_objc ())						\
+	{								\
+	  builtin_define ("_LANGUAGE_OBJECTIVE_C");			\
+	  builtin_define ("__LANGUAGE_OBJECTIVE_C");			\
+	  /* Bizarre, but needed at least for Irix.  */			\
+	  builtin_define_std ("LANGUAGE_C");				\
+	  builtin_define ("_LANGUAGE_C");				\
+	}								\
+									\
+      if (mips_abi == ABI_EABI)						\
+	builtin_define ("__mips_eabi");					\
+    }									\
+  while (0)
 
 /* Default target_flags if no switches are specified  */
 
@@ -591,7 +620,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define MIPS_ARCH_OPTION_SPEC \
   MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
 
-/* A spec that infers a -mips argument from an -march argument.  */
+/* A spec that infers a -mips argument from an -march argument,
+   or injects the default if no architecture is specified.  */
 
 #define MIPS_ISA_LEVEL_SPEC \
   "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
@@ -602,7 +632,14 @@ extern const struct mips_rtx_cost_data *mips_cost;
      %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
      %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
        |march=34k*|march=74k*: -mips32r2} \
-     %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64}}"
+     %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
+     %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
+
+/* A spec condition that matches 32-bit options.  It only works if
+   MIPS_ISA_LEVEL_SPEC has been applied.  */
+
+#define MIPS_32BIT_OPTION_SPEC \
+  "mips1|mips2|mips32*|mgp32"
 
 /* Support for a compile-time default CPU, et cetera.  The rules are:
    --with-arch is ignored if -march is specified or a -mips is specified
diff --git a/gcc/config/mips/sde.h b/gcc/config/mips/sde.h
new file mode 100644
index 0000000..14a1610
--- /dev/null
+++ b/gcc/config/mips/sde.h
@@ -0,0 +1,150 @@
+/* Definitions of target machine for GNU compiler.
+   MIPS SDE version.
+   Copyright (C) 2003, 2004
+   Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Let the -march option set soft-float.  */
+#define MIPS_MARCH_CONTROLS_SOFT_FLOAT 1
+
+#define DRIVER_SELF_SPECS						\
+  /* Make sure a -mips option is present.  This helps us to pick	\
+     the right multilib, and also makes the later specs easier		\
+     to write.  */							\
+  MIPS_ISA_LEVEL_SPEC,							\
+									\
+  /* If no ABI option is specified, infer one from the ISA level	\
+     or -mgp setting.  */						\
+  "%{!mabi=*: %{" MIPS_32BIT_OPTION_SPEC ": -mabi=32;: -mabi=n32}}",	\
+									\
+  /* Remove a redundant -mfp64 for -mabi=n32; we want the !mfp64	\
+     multilibs.  There's no need to check whether the architecture	\
+     is 64-bit; cc1 will complain if it isn't.  */			\
+  "%{mabi=n32: %<mfp64}"						\
+									\
+  /* Make sure that an endian option is always present.  This makes	\
+     things like LINK_SPEC easier to write.  */				\
+  "%{!EB:%{!EL:%(endian_spec)}}"
+
+/* Use trap rather than break for all but MIPS I ISA.  Force -no-mips16,
+   so that MIPS16 assembler code requires an explicit ".set mips16".
+   Very little hand-written MIPS16 assembler exists, and some build
+   systems expect code to be assembled as non-MIPS16 even if the
+   prevailing compiler flags select -mips16.  */
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "\
+%{!mips1:--trap} \
+%{fPIC|fpic|fPIE|fpie:%{!mips16*:-KPIC}} \
+%{mips16:-no-mips16}"
+
+#undef LINK_SPEC
+#define LINK_SPEC "\
+%(endian_spec) \
+%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
+%{bestGnum} \
+%{shared} %{non_shared} %{call_shared} \
+%{mabi=n32:-melf32%{EB:b}%{EL:l}tsmipn32} \
+%{mabi=64:-melf64%{EB:b}%{EL:l}tsmip} \
+%{mabi=32:-melf32%{EB:b}%{EL:l}tsmip}"
+
+#undef DEFAULT_SIGNED_CHAR
+#define DEFAULT_SIGNED_CHAR 0
+
+/* SDE-MIPS won't ever support SDB or MIPS debugging info.  */
+#undef SDB_DEBUGGING_INFO
+#undef MIPS_DEBUGGING_INFO
+
+/* Describe how we implement __builtin_eh_return.  */
+
+/* At the moment, nothing appears to use more than 2 EH data registers.
+   The chosen registers must not clash with the return register ($2),
+   EH_RETURN_STACKADJ ($3), or MIPS_EPILOGUE_TEMP ($5), and they must
+   be general MIPS16 registers.  Pick $6 and $7.  */
+#undef EH_RETURN_DATA_REGNO
+#define EH_RETURN_DATA_REGNO(N) \
+  ((N) < 2 ? 7 - (N) : INVALID_REGNUM)
+
+/* Use $5 as a temporary for both MIPS16 and non-MIPS16.  */
+#undef MIPS_EPILOGUE_TEMP_REGNUM
+#define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + 5)
+
+/* Using long will always be right for size_t and ptrdiff_t, since
+   sizeof(long) must equal sizeof(void *), following from the setting
+   of the -mlong64 option.  */
+#undef SIZE_TYPE
+#define SIZE_TYPE "long unsigned int"
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE "long int"
+
+/* Enable parsing of #pragma pack(push,<n>) and #pragma pack(pop).  */
+#define HANDLE_PRAGMA_PACK_PUSH_POP 1
+
+/* Use standard ELF-style local labels (not '$' as on early Irix).  */
+#undef LOCAL_LABEL_PREFIX
+#define LOCAL_LABEL_PREFIX "."
+
+/* Use periods rather than dollar signs in special g++ assembler names.  */
+#define NO_DOLLAR_IN_LABEL
+
+/* Attach a special .ident directive to the end of the file to identify
+   the version of GCC which compiled this code.  */
+#undef IDENT_ASM_OP
+#define IDENT_ASM_OP "\t.ident\t"
+
+/* Output #ident string into the ELF .comment section, so it doesn't
+   form part of the load image, and so that it can be stripped.  */
+#undef ASM_OUTPUT_IDENT
+#define ASM_OUTPUT_IDENT(STREAM, STRING) \
+  fprintf (STREAM, "%s\"%s\"\n", IDENT_ASM_OP, STRING);
+
+/* Currently we don't support 128bit long doubles, so for now we force
+   n32 to be 64bit.  */
+#undef LONG_DOUBLE_TYPE_SIZE
+#define LONG_DOUBLE_TYPE_SIZE 64
+
+#ifdef IN_LIBGCC2
+#undef LIBGCC2_LONG_DOUBLE_TYPE_SIZE
+#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
+#endif
+
+/* This version of _mcount does not pop 2 words from the stack.  */
+#undef FUNCTION_PROFILER
+#define FUNCTION_PROFILER(FILE, LABELNO)				\
+  {									\
+    fprintf (FILE, "\t.set\tnoat\n");					\
+    /* MIPS16 code passes saved $ra in $v1 instead of $at.  */		\
+    fprintf (FILE, "\tmove\t%s,%s\n",					\
+	     reg_names[GP_REG_FIRST + (TARGET_MIPS16 ? 3 : 1)],		\
+	     reg_names[GP_REG_FIRST + 31]);				\
+    fprintf (FILE, "\tjal\t_mcount\n");					\
+    fprintf (FILE, "\t.set\tat\n");					\
+  }
+
+/* Force all .init and .fini entries to be 32-bit, not mips16, so that
+   in a mixed environment they are all the same mode. The crti.asm and
+   crtn.asm files will also be compiled as 32-bit due to the
+   -no-mips16 flag in SUBTARGET_ASM_SPEC above. */
+#undef CRT_CALL_STATIC_FUNCTION
+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
+   asm (SECTION_OP "\n\
+	.set push\n\
+	.set nomips16\n\
+	jal " USER_LABEL_PREFIX #FUNC "\n\
+	.set pop\n\
+	" TEXT_SECTION_ASM_OP);
diff --git a/gcc/config/mips/t-elf b/gcc/config/mips/t-elf
index e66520b..55af208 100644
--- a/gcc/config/mips/t-elf
+++ b/gcc/config/mips/t-elf
@@ -10,26 +10,6 @@ $(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
 	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
 	-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
 
-LIB1ASMSRC = mips/mips16.S
-LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
-	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
-	_m16fltsisf _m16fix_truncsfsi \
-	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
-	_m16extsfdf2 _m16trdfsf2 \
-	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
-	_m16fltsidf _m16fix_truncdfsi \
-	_m16retsf _m16retdf \
-	_m16retsc _m16retdc \
-	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
-	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
-	_m16stubsf9 _m16stubsf10 \
-	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
-	_m16stubdf9 _m16stubdf10 \
-	_m16stubsc0 _m16stubsc1 _m16stubsc2 _m16stubsc5 _m16stubsc6 \
-	_m16stubsc9 _m16stubsc10 \
-	_m16stubdc0 _m16stubdc1 _m16stubdc2 _m16stubdc5 _m16stubdc6 \
-	_m16stubdc9 _m16stubdc10
-
 # We must build libgcc2.a with -G 0, in case the user wants to link
 # without the $gp register.
 TARGET_LIBGCC2_CFLAGS = -G 0
diff --git a/gcc/config/mips/t-isa3264 b/gcc/config/mips/t-isa3264
index fb5a55d..cec7e5e 100644
--- a/gcc/config/mips/t-isa3264
+++ b/gcc/config/mips/t-isa3264
@@ -10,26 +10,6 @@ $(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
 	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
 	-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
 
-LIB1ASMSRC = mips/mips16.S
-LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
-	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
-	_m16fltsisf _m16fix_truncsfsi \
-	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
-	_m16extsfdf2 _m16trdfsf2 \
-	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
-	_m16fltsidf _m16fix_truncdfsi \
-	_m16retsf _m16retdf \
-	_m16retsc _m16retdc \
-	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
-	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
-	_m16stubsf9 _m16stubsf10 \
-	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
-	_m16stubdf9 _m16stubdf10 \
-	_m16stubsc0 _m16stubsc1 _m16stubsc2 _m16stubsc5 _m16stubsc6 \
-	_m16stubsc9 _m16stubsc10 \
-	_m16stubdc0 _m16stubdc1 _m16stubdc2 _m16stubdc5 _m16stubdc6 \
-	_m16stubdc9 _m16stubdc10
-
 # We must build libgcc2.a with -G 0, in case the user wants to link
 # without the $gp register.
 TARGET_LIBGCC2_CFLAGS = -G 0
diff --git a/gcc/config/mips/t-libgcc-mips16 b/gcc/config/mips/t-libgcc-mips16
new file mode 100644
index 0000000..ba015e7
--- /dev/null
+++ b/gcc/config/mips/t-libgcc-mips16
@@ -0,0 +1,19 @@
+LIB1ASMSRC = mips/mips16.S
+LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
+	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
+	_m16fltsisf _m16fix_truncsfsi \
+	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
+	_m16extsfdf2 _m16trdfsf2 \
+	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
+	_m16fltsidf _m16fix_truncdfsi \
+	_m16retsf _m16retdf \
+	_m16retsc _m16retdc \
+	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
+	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
+	_m16stubsf9 _m16stubsf10 \
+	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
+	_m16stubdf9 _m16stubdf10 \
+	_m16stubsc0 _m16stubsc1 _m16stubsc2 _m16stubsc5 _m16stubsc6 \
+	_m16stubsc9 _m16stubsc10 \
+	_m16stubdc0 _m16stubdc1 _m16stubdc2 _m16stubdc5 _m16stubdc6 \
+	_m16stubdc9 _m16stubdc10
diff --git a/gcc/config/mips/t-r3900 b/gcc/config/mips/t-r3900
index 1245598..b95a373 100644
--- a/gcc/config/mips/t-r3900
+++ b/gcc/config/mips/t-r3900
@@ -1,23 +1,3 @@
-LIB1ASMSRC = mips/mips16.S
-LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
-	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
-	_m16fltsisf _m16fix_truncsfsi \
-	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
-	_m16extsfdf2 _m16trdfsf2 \
-	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
-	_m16fltsidf _m16fix_truncdfsi \
-	_m16retsf _m16retdf \
-	_m16retsc _m16retdc \
-	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
-	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
-	_m16stubsf9 _m16stubsf10 \
-	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
-	_m16stubdf9 _m16stubdf10 \
-	_m16stubsc0 _m16stubsc1 _m16stubsc2 _m16stubsc5 _m16stubsc6 \
-	_m16stubsc9 _m16stubsc10 \
-	_m16stubdc0 _m16stubdc1 _m16stubdc2 _m16stubdc5 _m16stubdc6 \
-	_m16stubdc9 _m16stubdc10
-
 # We must build libgcc2.a with -G 0, in case the user wants to link
 # without the $gp register.
 TARGET_LIBGCC2_CFLAGS = -G 0
diff --git a/gcc/config/mips/t-sde b/gcc/config/mips/t-sde
new file mode 100644
index 0000000..40c62dc
--- /dev/null
+++ b/gcc/config/mips/t-sde
@@ -0,0 +1,37 @@
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register. Use -fno-optimize-sibling-calls in case
+# we have a mixed mips16/non-mips16 environment where a plain "jump"
+# instuction won't work across the divide (no jx instruction).
+TARGET_LIBGCC2_CFLAGS = -G 0 -fno-optimize-sibling-calls
+
+MULTILIB_OPTIONS = EL/EB mips32/mips32r2/mips64 mips16 msoft-float/mfp64
+MULTILIB_DIRNAMES = el eb mips32 mips32r2 mips64 mips16 sof f64
+MULTILIB_MATCHES = EL=mel EB=meb
+
+# The -mfp64 option is only valid in conjunction with -mips32r2.
+ifneq ($(filter MIPS_ISA_DEFAULT=33,$(tm_defines)),)
+MULTILIB_EXCLUSIONS := mips32/mfp64 mips64/mfp64
+else
+MULTILIB_EXCLUSIONS := !mips32r2/mfp64
+endif
+
+# Don't build 64-bit MIPS16 multilibs.
+MULTILIB_EXCLUSIONS += mips16/mips64
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+
+# Build the multilibs.
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib