mips.md: Add unspec #2.

2001-09-15  Eric Christopher  <echristo@redhat.com>

	* config/mips/mips.md: Add unspec #2.
	(reload_indi): Use.
	(reload_outdi): Ditto.
	(reload_outsi): Ditto.
	(HILO_delay): New.

2001-09-15  Eric Christopher  <echristo@redhat.com>
	    Jason Eckhardt  <jle@redhat.com>

	* config.gcc: Add mipsisa32 target and mipsisa32-linux target.
	* config/mips/isa32-linux.h: New file.
	* config/mips/isa3264.h: Ditto.
	* config/mips/mips-protos.h: Add mips_hard_regno_nregs.
	* config/mips/mips.c (mips_hard_regno_nregs): Move here from mips.h.
	(output_block_mode): Support MEABI.
	(function_arg): Ditto. Fix floating point arg passing.
	(mips_va_start): Ditto.
	(override_options): Add isas 32 and 64, meabi, mips32 and mips64
	processors.
	(mips_asm_file_start): Add new section to pass abi to gdb.
	(function_arg_pass_by_reference): Support MEABI.
	(mips_parse_cpu): Support mips32 and mips64 processors.
	* config/mips/mips.h: Support ABI_MEABI, TARGET_MIPS4KC,
	TARGET_MIPS5KC.  Support isa32 and isa64.
	(processor_type): Add r4kc, r5kc, r20kc.
	(GENERATE_MULT3_SI): New.
	(GENERATE_MULT3_DI): Ditto.
	(GENERATE_MULT3): Remove.
	(ISA_HAS_64BIT_REGS): Add isa == 64.
	(ISA_HAS_8CC): Add mips_isa = 32 and 64.
	(ISA_HAS_MADD_MSUB): New.
	(ISA_HAS_CLZ_CLO): Ditto.
	(ISA_HAS_DCLZ_DCLO): Ditto.
	(ABI_GAS_ASM_SPEC): New.
	(GAS_ASM_SPEC): Use. Add support for mips32, mips64.
	(ASM_SPEC): Ditto.
	(LINK_SPEC): Ditto.
	(SUBTARGET_CC1_SPEC): Ditto.
	(SUBTARGET_CPP_SIZE_SPEC): Ditto.
	(PAD_VARARGS_DOWN): Support MEABI.
	(HARD_REGNO_NREGS): Move to mips.c.
	(ASM_OUTPUT_IDENT): Add #undef.
	* config/mips/mips.md: Add r4kc, r5kc, r20kc.
	(mulsi3): Use GENERATE_MULT3_SI.
	(mulsi3_mult3): Ditto.  Support mips32, mips64.
	(mul_acc_si): Use ISA_HAS_MADD_MSUB.
	(mul_sub_si): New pattern.
	(unnamed splitters): New.
	(muldi3): Use GENERATE_MULT3_DI.
	(muldi3_internal2): Ditto.
	(movdicc): Support mips32.
	* config/mips/t-isa3264: New file.

From-SVN: r45623

9 files changed, 736 insertions, 85 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b2e086e..89c2c3b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,58 @@
+2001-09-15  Eric Christopher  <echristo@redhat.com>
+
+	* config/mips/mips.md: Add unspec #2.
+	(reload_indi): Use.
+	(reload_outdi): Ditto.
+	(reload_outsi): Ditto.
+	(HILO_delay): New.
+
+2001-09-15  Eric Christopher  <echristo@redhat.com>
+	    Jason Eckhardt  <jle@redhat.com>
+
+	* config.gcc: Add mipsisa32 target and mipsisa32-linux target.
+	* config/mips/isa32-linux.h: New file.
+	* config/mips/isa3264.h: Ditto.
+	* config/mips/mips-protos.h: Add mips_hard_regno_nregs.
+	* config/mips/mips.c (mips_hard_regno_nregs): Move here from mips.h.
+	(output_block_mode): Support MEABI.
+	(function_arg): Ditto. Fix floating point arg passing.
+	(mips_va_start): Ditto.
+	(override_options): Add isas 32 and 64, meabi, mips32 and mips64
+	processors.
+	(mips_asm_file_start): Add new section to pass abi to gdb.
+	(function_arg_pass_by_reference): Support MEABI.
+	(mips_parse_cpu): Support mips32 and mips64 processors.
+	* config/mips/mips.h: Support ABI_MEABI, TARGET_MIPS4KC,
+	TARGET_MIPS5KC.  Support isa32 and isa64.
+	(processor_type): Add r4kc, r5kc, r20kc.
+	(GENERATE_MULT3_SI): New.
+	(GENERATE_MULT3_DI): Ditto.
+	(GENERATE_MULT3): Remove.
+	(ISA_HAS_64BIT_REGS): Add isa == 64.
+	(ISA_HAS_8CC): Add mips_isa = 32 and 64.
+	(ISA_HAS_MADD_MSUB): New.
+	(ISA_HAS_CLZ_CLO): Ditto.
+	(ISA_HAS_DCLZ_DCLO): Ditto.
+	(ABI_GAS_ASM_SPEC): New.
+	(GAS_ASM_SPEC): Use. Add support for mips32, mips64.
+	(ASM_SPEC): Ditto.
+	(LINK_SPEC): Ditto.
+	(SUBTARGET_CC1_SPEC): Ditto.
+	(SUBTARGET_CPP_SIZE_SPEC): Ditto.
+	(PAD_VARARGS_DOWN): Support MEABI.
+	(HARD_REGNO_NREGS): Move to mips.c.
+	(ASM_OUTPUT_IDENT): Add #undef.
+	* config/mips/mips.md: Add r4kc, r5kc, r20kc.
+	(mulsi3): Use GENERATE_MULT3_SI.
+	(mulsi3_mult3): Ditto.  Support mips32, mips64.
+	(mul_acc_si): Use ISA_HAS_MADD_MSUB.
+	(mul_sub_si): New pattern.
+	(unnamed splitters): New.
+	(muldi3): Use GENERATE_MULT3_DI.
+	(muldi3_internal2): Ditto.
+	(movdicc): Support mips32.
+	* config/mips/t-isa3264: New file.
+
 2001-09-15  Hans-Peter Nilsson  <hp@axis.com>
 
 	* rtl.h (FIND_REG_INC_NOTE) [HAVE_PRE_INCREMENT
@@ -81,7 +136,7 @@ Fri Sep 14 13:54:50 EDT 2001  John Wehle  (john@feith.com)
 	not already defined.
 	* config/arm/conix-elf.h: (USER_LABEL_PREFIX,
 	LOCAL_LABEL_PREFIX, MAKE_DECL_ONE_ONLY, UNIQUE_SECTION):
-	Remove duplicate definition. 
+	Remove duplicate definition.
 	(READONLY_DATA_SECTION, SUBTARGET_EXTRA_SECTION,
 	(SUBTARGET_EXTRA_SECTION_FUNCTION, RDATA_SECTION_ASM_OP,
 	(RDATA_SECTION_FUNCTION): Remove redundant definition.
@@ -113,6 +168,7 @@ Fri Sep 14 13:54:50 EDT 2001  John Wehle  (john@feith.com)
 	* crti.asm: New file.
 	* crtn.asm: New file.
 
+>>>>>>> 1.11331
 2001-09-13  Neil Booth  <neil@daikokuya.demon.co.uk>
 
 	* c-parse.in (_yylex): Use _cpp_backup_tokens.
@@ -170,7 +226,7 @@ Fri Sep 14 13:54:50 EDT 2001  John Wehle  (john@feith.com)
 	* sdbout.c (plain_type_1, sdbout_end_function,
 	sdbout_end_epilogue): Likewise.
 	* varasm.c (decode_reg_name): Likewise.
-	
+
 	* 1750a.c (mod_regno_adjust): Likewise.
 	* alpha.c (alpha_write_one_linkage,
 	unicosmk_output_default_externs): Likewise.
@@ -225,7 +281,7 @@ Fri Sep 14 13:54:50 EDT 2001  John Wehle  (john@feith.com)
 
 	* fixinc/inclhack.def(hpux11_size_t): Keep HP-UX headers from
 	defining __size_t and leaving size_t undefined.
-	
+
 2001-09-12  Diego Novillo  <dnovillo@redhat.com>
 
 	* basic-block.h (expunge_block): Declare.
@@ -264,7 +320,7 @@ Fri Sep 14 13:54:50 EDT 2001  John Wehle  (john@feith.com)
 	* toplev.c (decode_g_option): Likewise.
 	* tradcpp.c (output_deps): Likewise.
 	* varasm.c (decode_reg_name): Likewise.
-	
+
 	* arm.c (arm_condition_codes, strings_fpa, thumb_condition_code):
 	Const-ification.
 	* arm.md: Likewise.
@@ -514,7 +570,7 @@ Tue Sep 11 11:37:52 CEST 2001  Jan Hubicka  <jh@suse.cz>
 	Unicos/Mk versions.
 	(*divmodsi_internal, *divmoddi_internal): Disable for
 	TARGET_ABI_UNICOSMK.
-	(unaligned_extend?idi, unaligned_load?i, unaligned_store?i): Split in 
+	(unaligned_extend?idi, unaligned_load?i, unaligned_store?i): Split in
 	little-endian and big-endian versions.
 	(ext, ins, msk): Likewise.
 	(extv, extzv, insv): Support big-endian mode.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index dc731f7..4b4779c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -92,10 +92,10 @@
 #
 #  c_target_objs	List of extra target-dependant objects that be
 #			linked into the C compiler only.
-#  
+#
 #  cxx_target_objs	List of extra target-dependant objects that be
 #			linked into the C++ compiler only.
-#  
+#
 #  build_xm_defines	List of macros to define when compiling for the
 #			build machine.
 #
@@ -252,7 +252,7 @@ case $machine in
 *-*-*aout*)
 	use_collect2=yes
 	;;
-esac	
+esac
 
 # Common parts for GNU/Linux, GNU/Hurd, OpenBSD and FreeBSD systems.
 case $machine in
@@ -401,7 +401,7 @@ a29k-*-*)			# Default a29k environment.
 alpha*-*-unicosmk*)
 	use_collect2=yes
 	tm_file="${tm_file} alpha/unicosmk.h"
-	
+
 	# Don't include t-ieee for now because we don't support that yet
 	# tmake_file="alpha/t-ieee"
 	tmake_file="alpha/t-unicosmk"
@@ -471,7 +471,7 @@ alpha*-*-openbsd*)
 	target_cpu_default="MASK_GAS"
 	tmake_file="alpha/t-alpha alpha/t-ieee"
 	;;
-	
+
 alpha*-dec-osf*)
 	xm_defines=POSIX
 	if test x$stabs = xyes
@@ -597,7 +597,7 @@ arm*-*-aout)
 arm*-*-ecos-elf)
 	tm_file="elfos.h arm/unknown-elf.h arm/elf.h arm/ecos-elf.h"
 	tmake_file=arm/t-arm-elf
-	;; 
+	;;
 arm*-*-elf)
 	tm_file="elfos.h arm/unknown-elf.h arm/elf.h"
 	tmake_file=arm/t-arm-elf
@@ -634,7 +634,7 @@ c34-convex-*)
 	use_collect2=yes
 	;;
 c38-convex-*)
-	target_cpu_default=16		
+	target_cpu_default=16
 	use_collect2=yes
 	;;
 c4x-*-rtems*)
@@ -911,12 +911,12 @@ hppa*-*-lites*)
 	;;
 hppa*-*-mpeix*)
 	tm_file="${tm_file} pa/pa32-regs.h pa/long_double.h pa/som.h pa/pa-mpeix.h"
-	xmake_file=pa/x-pa-mpeix 
-	echo "You must use gas. Assuming it is already installed." 
+	xmake_file=pa/x-pa-mpeix
+	echo "You must use gas. Assuming it is already installed."
 	gas=yes
 	install_headers_dir=install-headers-tar
-	use_collect2=yes 
-	;; 
+	use_collect2=yes
+	;;
 i370-*-opened*)			 # IBM 360/370/390 Architecture
 	xm_defines='POSIX FATAL_EXIT_CODE=12'
 	tm_file=i370/oe.h
@@ -1117,7 +1117,7 @@ i[34567]86-*-linux*aout*)	# Intel 80386's running GNU/Linux
 i[34567]86-*-linux*libc1)	# Intel 80386's running GNU/Linux
 				# with ELF format using the
 				# GNU/Linux C library 5
-	xmake_file=x-linux	
+	xmake_file=x-linux
 	tm_file="i386/i386.h i386/att.h linux.h i386/linux.h"
 	tmake_file="t-slibgcc-elf-ver t-linux t-linux-gnulibc1 i386/t-crtstuff"
 	extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
@@ -2215,7 +2215,11 @@ mips*-*-linux*)				# Linux MIPS, either endian.
 	xmake_file=x-linux
 	tm_file="linux.h mips/linux.h"
 	case $machine in
-	       mips*el-*)  tm_file="mips/little.h $tm_file" ;;
+		mipsisa32el-*)
+			tm_file="mips/little.h $tm_file mips/isa32-linux.h";;
+                mipsisa32-*)
+			tm_file="$tm_file mips/isa32-linux.h";;
+	       	mips*el-*)  tm_file="mips/little.h $tm_file" ;;
 	esac
 	tmake_file="t-slibgcc-elf-ver t-linux"
 	extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
@@ -2434,6 +2438,10 @@ mips-*-ecoff*)
 	fi
 	tmake_file=mips/t-ecoff
 	;;
+mipsisa32-*-elf*)
+	tm_file="mips/isa3264.h mips/abi64.h"
+	tmake_file=mips/t-isa3264
+	;;
 mipsel-*-elf*)
 	tm_file="mips/elfl.h"
 	tmake_file=mips/t-elf
@@ -2789,7 +2797,7 @@ rs6000-*-lynxos*)
 	tmake_file=rs6000/t-rs6000
 	use_collect2=yes
 	;;
-s390-*-linux*)	
+s390-*-linux*)
 	xmake_file=x-linux
 	tm_file=s390/linux.h
 	tmake_file="t-slibgcc-elf-ver t-linux s390/t-linux"
@@ -2798,7 +2806,7 @@ s390-*-linux*)
 		thread_file='posix'
 	fi
 	;;
-s390x-*-linux*)	
+s390x-*-linux*)
 	xmake_file=x-linux
 	tm_file=s390/linux64.h
 	tmake_file="t-slibgcc-elf-ver t-linux s390/t-linux"
@@ -3089,7 +3097,7 @@ sparc86x-*-aout*)
 	tm_file="sparc/sp86x-aout.h aoutos.h libgloss.h"
 	tmake_file=sparc/t-sp86x
 	;;
-sparc86x-*-elf*)	
+sparc86x-*-elf*)
 	tm_file="sparc/sol2.h sparc./elf.h sparc/sp86x-elf.h"
 	tmake_file=sparc/t-sp86x
         extra_parts="crtbegin.o crtend.o"
@@ -3272,7 +3280,7 @@ alpha*-*-*)
 			target_cpu_default2="MASK_CPU_EV5"
 			;;
 	esac
-			
+
 	if test x$gas = xyes
 	then
 		if test "$target_cpu_default2" = ""
diff --git a/gcc/config/mips/isa32-linux.h b/gcc/config/mips/isa32-linux.h
new file mode 100644
index 0000000..a03b79a
--- /dev/null
+++ b/gcc/config/mips/isa32-linux.h
@@ -0,0 +1,29 @@
+/* Definitions for MIPS32 running Linux-based GNU systems with ELF format.
+   Copyright (C) 2001 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#undef TARGET_VERSION
+#if TARGET_ENDIAN_DEFAULT == 0
+#define TARGET_VERSION fprintf (stderr, " (MIPS32el GNU/Linux with ELF)");
+#else
+#define TARGET_VERSION fprintf (stderr, " (MIPS32 GNU/Linux with ELF)");
+#endif
+
+#undef MIPS_ISA_DEFAULT
+#define MIPS_ISA_DEFAULT 32
diff --git a/gcc/config/mips/isa3264.h b/gcc/config/mips/isa3264.h
new file mode 100644
index 0000000..cd25e55
--- /dev/null
+++ b/gcc/config/mips/isa3264.h
@@ -0,0 +1,148 @@
+/* Definitions of target machine for GNU compiler.
+   MIPS 32 and MIPS 64 version.
+   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#ifndef MIPS_ISA_DEFAULT
+#define MIPS_ISA_DEFAULT 32
+#endif
+
+#ifndef MIPS_ABI_DEFAULT
+#define MIPS_ABI_DEFAULT ABI_MEABI
+#endif
+
+#ifndef MIPS_ENABLE_EMBEDDED_O32
+#define MIPS_ENABLE_EMBEDDED_O32 1
+#endif
+
+#ifndef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+#endif
+
+#include "mips/elf.h"
+
+/* This must be done after including mips.h so that the
+   ABI_{EABI,O64,O32,...} are #defined. */
+
+#if MIPS_ABI_DEFAULT == ABI_EABI
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mabi=eabi|!mabi=*:\
+  %{mips1|mips2|mips32|mlong32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+  %{!mips1:%{!mips2:%{!mips32:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}} \
+%{mabi=o64:\
+ %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+ %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
+%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+"
+#elif MIPS_ABI_DEFAULT == ABI_O64
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mabi=eabi:\
+  %{mips1|mips2|mips32|mlong32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+  %{!mips1:%{!mips2:%{!mips32:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}} \
+%{mabi=o64|!mabi=*:\
+ %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+ %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
+%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+"
+
+#elif MIPS_ABI_DEFAULT == ABI_32
+#if MIPS_ISA_DEFAULT == 3 || MIPS_ISA_DEFAULT == 4 || MIPS_ISA_DEFAULT == 5 || MIPS_ISA_DEFAULT == 64
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mabi=eabi:\
+  %{mips1|mips2|mips32|mlong32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+  %{!mips1:%{!mips2:%{!mips32:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}} \
+%{mabi=o64|!!mabi=*:\
+ %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+ %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
+%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+"
+#else /* not a 64bit default ISA */
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mabi=eabi:\
+  %{mips3|mips4|mips5|mips64|mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+  %{!mips3:%{!mips4:%{!mips5:%{!mips64:%{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}} \
+%{mabi=o64:\
+ %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+ %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
+%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+%{!mabi=*:\
+ %{mips3|mips4|mips5|mips64:\
+  %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+  %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
+ %{!mips3:%{!mips4:%{!mips5:%{!mips64:\
+  -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}} \
+"
+#endif /* ISA */
+
+#elif MIPS_ABI_DEFAULT == ABI_MEABI
+/* For MEABI, don't link with crt0 files, let the linker start files specify
+   the appropriate crt0 file.  */
+#undef  STARTFILE_SPEC
+#define STARTFILE_SPEC "crti%O%s crtbegin%O%s %{!mno-crt0: }"
+
+/*
+   The MIPS_ISA_DEFAULT test is for EABI, in which the size of longs depends on
+   the ISA.
+
+   For MEABI the size of longs is always 32bits.  If long64 is specified then
+   we honor that.  The errors for long64 & long32 is because while CC1 can
+   handle overriding mlong32 with mlong64 and vise-versa, the specs cannot. */
+
+#if MIPS_ISA_DEFAULT == 3 || MIPS_ISA_DEFAULT == 4 || MIPS_ISA_DEFAULT == 5 || MIPS_ISA_DEFAULT == 64
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mabi=meabi:\
+  %{mips1|mips2|mips32|mlong32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+  %{!mips1:%{!mips2:%{!mips32:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}} \
+%{mabi=o64:\
+ %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
+  %{mlong32:%e-mlong32 and -mlong64 can not both be specified.}} \
+ %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int }} \
+%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+%{mabi=meabi|!mabi=*:\
+ %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
+  %{mlong32:%e-mlong32 and -mlong64 can not both be specified.}} \
+ %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int }} \
+"
+
+#else /* not a 64bit default ISA */
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mabi=meabi:\
+  %{mips3|mips4|mips5|mips64|mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+  %{!mips3:%{!mips4:%{!mips5:%{!mips64:%{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}} \
+%{mabi=o64:\
+ %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
+  %{mlong32:%e-mlong32 and -mlong64 can not both be specified.}} \
+ %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int }} \
+%{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+%{mabi=meabi|!mabi=*:\
+ %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
+  %{mlong32:%e-mlong32 and -mlong64 can not both be specified.}} \
+ %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int }} \
+"
+#endif /* ISA */
+
+#endif /* ABI */
+
+/* eof */
diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 5cc409c..57011ae 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -53,6 +53,7 @@ extern int		mips_output_external_libcall PARAMS ((FILE *, const char *));
 
 
 #ifdef TREE_CODE
+extern unsigned int	mips_hard_regno_nregs PARAMS ((int, enum machine_mode));
 extern struct rtx_def *	function_arg PARAMS ((CUMULATIVE_ARGS *, enum machine_mode, tree, int));
 extern void		function_arg_advance PARAMS ((CUMULATIVE_ARGS *, enum machine_mode, tree, int));
 extern int		function_arg_partial_nregs PARAMS ((CUMULATIVE_ARGS *, enum machine_mode, tree, int));
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 483cc23..dee6503 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1383,7 +1383,7 @@ mips_legitimate_address_p (mode, xinsn, strict)
 	         (set (blah:DI) (plus x y)).  */
 	      && (!TARGET_64BIT
 		  || (code1 == CONST_INT
-		      && trunc_int_for_mode (INTVAL (xplus1), 
+		      && trunc_int_for_mode (INTVAL (xplus1),
 					     SImode) == INTVAL (xplus1)))
 	      && !TARGET_MIPS16)
 	    return 1;
@@ -3536,7 +3536,9 @@ output_block_move (insn, operands, num_regs, move_type)
      constant addresses into registers when generating N32/N64 code, just
      in case we might emit an unaligned load instruction.  */
   if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
-		       || mips_abi == ABI_N32 || mips_abi == ABI_64))
+		       || mips_abi == ABI_MEABI
+		       || mips_abi == ABI_N32
+		       || mips_abi == ABI_64))
     {
       if (CONSTANT_P (src_reg))
 	{
@@ -3994,6 +3996,11 @@ function_arg (cum, mode, type, named)
 	  arg_words = &cum->fp_arg_words;
 	  regbase = FP_ARG_FIRST;
 	}
+      /* The MIPS eabi says only structures containing doubles get passed in a
+         fp register, so force a structure containing a float to be passed in
+         the integer registers.  */
+      else if (mips_abi == ABI_MEABI && struct_p)
+	regbase = GP_ARG_FIRST;
       else
 	regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
       break;
@@ -4063,11 +4070,30 @@ function_arg (cum, mode, type, named)
       if (regbase == -1)
 	abort ();
 
-      if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
-	  || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named
+      if (! type || TREE_CODE (type) != RECORD_TYPE
+	  || mips_abi == ABI_32  || mips_abi == ABI_EABI
+	  || mips_abi == ABI_O64 || mips_abi == ABI_MEABI
+	  || ! named
 	  || ! TYPE_SIZE_UNIT (type)
 	  || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
-	ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
+	{
+
+	  unsigned int arg_reg = (regbase + *arg_words + bias);
+	  ret = gen_rtx_REG (mode, arg_reg);
+	  if (mips_abi == ABI_MEABI
+	      && regbase == FP_ARG_FIRST
+	      && ! cum->prototype)
+	    {
+              /* To make K&R varargs work we need to pass floating
+                 point arguments in both integer and FP registers.  */
+              ret = gen_rtx_PARALLEL (mode,
+				      gen_rtvec (2,
+						 gen_rtx_EXPR_LIST (VOIDmode,
+								    gen_rtx_REG (mode,
+										 arg_reg + GP_ARG_FIRST - FP_ARG_FIRST),
+								    const0_rtx),                                                gen_rtx_EXPR_LIST (VOIDmode, ret, const0_rtx)));
+            }
+	}
       else
 	{
 	  /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
@@ -4124,6 +4150,7 @@ function_arg (cum, mode, type, named)
 		  if (field
 		      && int_bit_position (field) == bitpos
 		      && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
+		      && !TARGET_SOFT_FLOAT
 		      && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
 		    reg = gen_rtx_REG (DFmode,
 				       regno + FP_ARG_FIRST - GP_ARG_FIRST);
@@ -4164,7 +4191,9 @@ function_arg (cum, mode, type, named)
 	 calling convention for now.  */
 
       if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
-	  && ! TARGET_64BIT && mips_abi != ABI_EABI)
+	  && ! TARGET_64BIT
+	  && mips_abi != ABI_EABI
+	  && mips_abi != ABI_MEABI)
 	{
 	  rtx amount = GEN_INT (BITS_PER_WORD
 				- int_size_in_bytes (type) * BITS_PER_UNIT);
@@ -4454,6 +4483,8 @@ mips_va_start (stdarg_p, valist, nextarg)
 	     and both iris5.h and iris6.h define _MIPS_SIM.  */
 	  if (mips_abi == ABI_N32 || mips_abi == ABI_64)
  	    ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
+	  else if (mips_abi == ABI_MEABI)
+	    ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
 	  else
 	    ofs = -UNITS_PER_WORD;
 	}
@@ -4764,7 +4795,10 @@ override_options ()
 	      mips_isa = MIPS_ISA_DEFAULT;
 	    }
 	}
-      else if (mips_isa < 1 || mips_isa > 4)
+      else if (mips_isa < 1
+	       || (mips_isa > 4
+		   && mips_isa != 32
+		   && mips_isa != 64))
 	{
 	  error ("-mips%d not supported", mips_isa);
 	  mips_isa = 1;
@@ -4791,17 +4825,26 @@ override_options ()
     mips_abi = ABI_64;
   else if (! strcmp (mips_abi_string, "eabi"))
     mips_abi = ABI_EABI;
+  else if (! strcmp (mips_abi_string, "meabi"))
+    mips_abi = ABI_MEABI;
   else
     error ("bad value (%s) for -mabi= switch", mips_abi_string);
 
   /* A specified ISA defaults the ABI if it was not specified.  */
   if (mips_abi_string == 0 && mips_isa_string
-      && mips_abi != ABI_EABI && mips_abi != ABI_O64)
+      && mips_abi != ABI_EABI
+      && mips_abi != ABI_O64
+      && mips_abi != ABI_MEABI)
     {
-      if (! ISA_HAS_64BIT_REGS)
-	mips_abi = ABI_32;
+      if (mips_isa == 64)
+	mips_abi = ABI_O64;
       else
-	mips_abi = ABI_64;
+	{
+	  if (! ISA_HAS_64BIT_REGS)
+	    mips_abi = ABI_32;
+	  else
+	    mips_abi = ABI_64;
+	}
     }
 
 #ifdef MIPS_CPU_STRING_DEFAULT
@@ -4894,6 +4937,14 @@ override_options ()
 	  mips_arch_string = "8000";
 	  mips_arch = PROCESSOR_R8000;
 	  break;
+	case 32:
+          mips_arch_string = "4kc";
+          mips_arch = PROCESSOR_R4KC;
+          break;
+        case 64:
+          mips_arch_string = "5kc";
+          mips_arch = PROCESSOR_R5KC;
+          break;
 	}
     }
   else
@@ -4930,6 +4981,14 @@ override_options ()
 	  mips_tune_string = "8000";
 	  mips_tune = PROCESSOR_R8000;
 	  break;
+	case 32:
+	  mips_arch_string = "4kc";
+	  mips_arch = PROCESSOR_R4KC;
+	  break;
+	case 64:
+	  mips_arch_string = "5kc";
+	  mips_arch = PROCESSOR_R5KC;
+	  break;
 	}
 
     }
@@ -4943,16 +5002,22 @@ override_options ()
 	}
     }
 
-   /* Handle processor configuration based on architecture.  */
-   if (TARGET_MIPS4100 || TARGET_MIPS3900)
-     target_flags |= MASK_SOFT_FLOAT;
+  /* Handle processor configuration based on architecture.  */
+  if (TARGET_MIPS4100
+      || TARGET_MIPS3900
+      || TARGET_MIPS4KC
+      || TARGET_MIPS5KC)
+    target_flags |= MASK_SOFT_FLOAT;
 
 
   if ((mips_arch == PROCESSOR_R3000 && (mips_isa != 1))
+      || (mips_arch == PROCESSOR_R4KC && mips_isa != 32)
+      || ((mips_arch == PROCESSOR_R5KC
+	   || mips_arch == PROCESSOR_R20KC) && mips_isa != 64)
       || (mips_arch == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
       || ((mips_arch == PROCESSOR_R4000
-           || mips_arch == PROCESSOR_R4100
-           || mips_arch == PROCESSOR_R4300
+	   || mips_arch == PROCESSOR_R4100
+	   || mips_arch == PROCESSOR_R4300
 	   || mips_arch == PROCESSOR_R4600
 	   || mips_arch == PROCESSOR_R4650)
 	  && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
@@ -5160,7 +5225,14 @@ override_options ()
 	    temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
 
 	  else if (FP_REG_P (regno))
-	    temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
+	    temp = ((TARGET_FLOAT64 || ((regno & 1) == 0)
+		      /* I think this change is OK regardless of abi, but
+                        I'm being cautions untill I can test this more.
+                        HARD_REGNO_MODE_OK is about whether or not you
+                        can move to and from a register without changing
+                        the value, not about whether math works on the
+                        register.  */
+                     || (mips_abi == ABI_MEABI && size <= 4))
 		    && (class == MODE_FLOAT
 			|| class == MODE_COMPLEX_FLOAT
 			|| (TARGET_DEBUG_H_MODE && class == MODE_INT))
@@ -5866,7 +5938,6 @@ mips_output_lineno (stream, line)
 	       LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
 	       LOCAL_LABEL_PREFIX, sym_lineno);
     }
-
   else
     {
       fprintf (stream, "\n\t%s.loc\t%d %d\n",
@@ -6021,6 +6092,8 @@ void
 mips_asm_file_start (stream)
      FILE *stream;
 {
+  const char * abi_string = NULL;
+
   ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
 
   /* Versions of the MIPS assembler before 2.20 generate errors if a branch
@@ -6031,6 +6104,35 @@ mips_asm_file_start (stream)
   if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
     fprintf (stream, "\t.set\tnobopt\n");
 
+#ifdef OBJECT_FORMAT_ELF
+  /* Generate a special section to describe the ABI switches used to produce
+     the resultant binary.  This used to be done by the assembler setting bits
+     in the ELF header's flags field, but we have run out of bits.  GDB needs
+     this information in order to be able to correctly debug these binaries.
+     See the function mips_gdbarch_init() in gdb/mips-tdep.c.  */
+  switch (mips_abi)
+    {
+    case ABI_32:   abi_string = "abi32"; break;
+    case ABI_N32:  abi_string = "abiN32"; break;
+    case ABI_64:   abi_string = "abi64"; break;
+    case ABI_O64:  abi_string = "abiO64"; break;
+    case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
+    case ABI_MEABI:abi_string = TARGET_64BIT ? "meabi64" : "meabi32"; break;
+    default:
+      abort ();
+    }
+  /* Note - we use fprintf directly rather than called named_section()
+     because in this way we can avoid creating an allocated section.  We
+     do not want this section to take up any space in the running
+     executable.  */
+  fprintf (stream, "\t.section .mdebug.%s\n", abi_string);
+
+  /* Restore the default section.  */
+  fprintf (stream, "\t.previous\n");
+#endif
+
+
+
   /* Generate the pseudo ops that System V.4 wants.  */
 #ifndef ABICALLS_ASM_OP
 #define ABICALLS_ASM_OP "\t.abicalls"
@@ -6115,7 +6217,6 @@ copy_file_data (to, from)
 {
   char buffer[8192];
   size_t len;
-
   rewind (from);
   if (ferror (from))
     fatal_io_error ("can't rewind temp file");
@@ -7910,7 +8011,8 @@ function_arg_pass_by_reference (cum, mode, type, named)
      to prevent it, or add code to function.c to properly handle the case.  */
   /* ??? cum can be NULL when called from mips_va_arg.  The problem handled
      here hopefully is not relevant to mips_va_arg.  */
-  if (cum && MUST_PASS_IN_STACK (mode, type))
+  if (cum && MUST_PASS_IN_STACK (mode, type)
+      && mips_abi != ABI_MEABI)
      {
        /* Don't pass the actual CUM to FUNCTION_ARG, because we would
 	  get double copies of any offsets generated for small structs
@@ -9714,6 +9816,8 @@ mips_parse_cpu (cpu_string)
     case '2':
       if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
 	cpu = PROCESSOR_R3000;
+      else if (!strcmp (p, "20kc") || !strcmp (p, "20Kc") )
+        cpu = PROCESSOR_R20KC;
       break;
 
     case '3':
@@ -9742,11 +9846,20 @@ mips_parse_cpu (cpu_string)
 	cpu = PROCESSOR_R4600;
       else if (!strcmp (p, "4650"))
 	cpu = PROCESSOR_R4650;
+      /* The 4kc and 4kp processor cores are the same for
+	 scheduling purposes; they both implement the MIPS32
+	 ISA and only differ in their memory management
+	 methods.  */
+      else if (!strcmp (p, "4kc") || !strcmp (p, "4Kc")
+               || !strcmp (p, "4kp") || !strcmp (p, "4Kp") )
+	cpu = PROCESSOR_R4KC;
       break;
 
     case '5':
       if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
 	cpu = PROCESSOR_R5000;
+      else if (!strcmp (p, "5kc") || !strcmp (p, "5Kc") )
+          cpu = PROCESSOR_R5KC;
       break;
 
     case '6':
@@ -9864,6 +9977,17 @@ mips_unique_section (decl, reloc)
   DECL_SECTION_NAME (decl) = build_string (len, string);
 }
 
+unsigned int
+mips_hard_regno_nregs (regno, mode)
+    int regno;
+    enum machine_mode mode;
+{
+  if (! FP_REG_P (regno))
+    return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
+  else
+    return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
+}
+
 
 #ifdef TARGET_IRIX6
 /* Output assembly to switch to section NAME with attribute FLAGS.  */
@@ -9887,7 +10011,6 @@ iris6_asm_named_section_1 (name, flags, align)
     sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
   if (strcmp (name, ".debug_frame") == 0)
     sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
-
   if (flags & SECTION_DEBUG)
     sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
   else if (flags & SECTION_BSS)
@@ -9980,7 +10103,7 @@ iris6_asm_output_align (file, log)
    but takes it from the first .section directive seen.  Play yet more
    file switching games so that we can emit a .section directive at the
    beginning of the file with the proper alignment attached.  */
-   
+
 void
 iris6_asm_file_start (stream)
      FILE *stream;
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index fb54bcd..dfb8aff 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -67,7 +67,10 @@ enum processor_type {
   PROCESSOR_R4600,
   PROCESSOR_R4650,
   PROCESSOR_R5000,
-  PROCESSOR_R8000
+  PROCESSOR_R8000,
+  PROCESSOR_R4KC,
+  PROCESSOR_R5KC,
+  PROCESSOR_R20KC
 };
 
 /* Recast the cpu class to be the cpu attribute.  */
@@ -84,6 +87,18 @@ enum processor_type {
 #define ABI_64  2
 #define ABI_EABI 3
 #define ABI_O64  4
+/* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
+   which is not the same as the above EABI (defined by Cygnus,
+   Greenhills, and Toshiba?).  MEABI is not yet complete or published,
+   but at this point it looks like N32 as far as calling conventions go,
+   but allows for either 32 or 64 bit registers.
+
+   Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
+   EABI the legacy EABI.  In the end we may end up calling both ABI's
+   EABI but give them different version numbers, but for now I'm going
+   with different names. */
+#define ABI_MEABI 5
+
 
 #ifndef MIPS_ABI_DEFAULT
 /* We define this away so that there is no extra runtime cost if the target
@@ -339,6 +354,8 @@ extern void		sbss_section PARAMS ((void));
 #define TARGET_MIPS4000             (mips_arch == PROCESSOR_R4000)
 #define TARGET_MIPS4100             (mips_arch == PROCESSOR_R4100)
 #define TARGET_MIPS4300             (mips_arch == PROCESSOR_R4300)
+#define TARGET_MIPS4KC              (mips_arch == PROCESSOR_R4KC)
+#define TARGET_MIPS5KC              (mips_arch == PROCESSOR_R5KC)
 
 /* Scheduling target defines.  */
 #define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
@@ -542,8 +559,16 @@ extern void		sbss_section PARAMS ((void));
 #        if MIPS_ISA_DEFAULT == 4
 #          define MULTILIB_ISA_DEFAULT "mips4"
 #        else
+#          if MIPS_ISA_DEFAULT == 32
+#            define MULTILIB_ISA_DEFAULT "mips32"
+#          else
+#            if MIPS_ISA_DEFAULT == 64
+#              define MULTILIB_ISA_DEFAULT "mips64"
+#            else
 #          define MULTILIB_ISA_DEFAULT "mips1"
+#         endif
 #        endif
+#       endif
 #      endif
 #    endif
 #  endif
@@ -607,9 +632,15 @@ extern void		sbss_section PARAMS ((void));
 
 #define GENERATE_BRANCHLIKELY  (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
 
-/* Generate three-operand multiply instructions for both SImode and DImode.  */
-#define GENERATE_MULT3         (TARGET_MIPS3900				\
-				&& !TARGET_MIPS16)
+/* Generate three-operand multiply instructions for SImode.  */
+#define GENERATE_MULT3_SI       ((TARGET_MIPS3900                       \
+                                  || mips_isa == 32                     \
+                                  || mips_isa == 64)                    \
+                                 && !TARGET_MIPS16)
+
+/* Generate three-operand multiply instructions for DImode.  */
+#define GENERATE_MULT3_DI       ((TARGET_MIPS3900)                      \
+				 && !TARGET_MIPS16)
 
 /* Macros to decide whether certain features are available or not,
    depending on the instruction set architecture level.  */
@@ -618,8 +649,9 @@ extern void		sbss_section PARAMS ((void));
 #define HAVE_SQRT_P()		(mips_isa != 1)
 
 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
-#define ISA_HAS_64BIT_REGS	(mips_isa == 3 || mips_isa == 4 	\
-                                )
+#define ISA_HAS_64BIT_REGS	(mips_isa == 3          \
+				 || mips_isa == 4 	\
+                                 || mips_isa == 64)
 
 /* ISA has branch likely instructions (eg. mips2). */
 /* Disable branchlikely for tx39 until compare rewrite.  They haven't
@@ -629,7 +661,8 @@ extern void		sbss_section PARAMS ((void));
 
 /* ISA has the conditional move instructions introduced in mips4. */
 #define ISA_HAS_CONDMOVE        (mips_isa == 4				\
-				 )
+				 || mips_isa == 32                      \
+				 || mips_isa == 64)
 
 /* ISA has just the integer condition move instructions (movn,movz) */
 #define ISA_HAS_INT_CONDMOVE     0
@@ -639,7 +672,8 @@ extern void		sbss_section PARAMS ((void));
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
    branch on CC, and move (both FP and non-FP) on CC. */
 #define ISA_HAS_8CC		(mips_isa == 4				\
-				)
+                         	 || mips_isa == 32                      \
+				 || mips_isa == 64)
 
 
 /* This is a catch all for the other new mips4 instructions: indexed load and
@@ -651,10 +685,25 @@ extern void		sbss_section PARAMS ((void));
 /* ISA has conditional trap instructions.  */
 #define ISA_HAS_COND_TRAP	(mips_isa >= 2)
 
+/* ISA has multiply-accumulate instructions, madd and msub.  */
+#define ISA_HAS_MADD_MSUB       (mips_isa == 32                         \
+                                || mips_isa == 64                       \
+                                )
+
 /* ISA has nmadd and nmsub instructions.  */
 #define ISA_HAS_NMADD_NMSUB	(mips_isa == 4				\
 				)
 
+/* ISA has count leading zeroes/ones instruction (not implemented).  */
+#define ISA_HAS_CLZ_CLO         (mips_isa == 32                         \
+                                || mips_isa == 64                       \
+                                )
+
+/* ISA has double-word count leading zeroes/ones instruction (not
+   implemented).  */
+#define ISA_HAS_DCLZ_DCLO       (mips_isa == 64)
+
+
 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
    -mips2 sets -mfp32 and -mgp32.  This can be overridden by an explicit
    -mfp32, -mfp64, -mgp32 or -mgp64.  -mfp64 sets MASK_FLOAT64 in
@@ -670,10 +719,7 @@ extern void		sbss_section PARAMS ((void));
 
 /* Switch  Recognition by gcc.c.  Add -G xx support */
 
-#ifdef SWITCH_TAKES_ARG
-#undef SWITCH_TAKES_ARG
-#endif
-
+#undef  SWITCH_TAKES_ARG
 #define SWITCH_TAKES_ARG(CHAR)						\
   (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
 
@@ -822,7 +868,39 @@ while (0)
 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
    assembler.  */
 
-#define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
+#define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips2}}"
+
+#ifndef MIPS_ABI_DEFAULT
+#define ABI_GAS_ASM_SPEC "\
+%{mabi=*} \
+%{!mabi=*:%{mips1|mips2|mips32:-mabi=32} %{!mips1:%{!mips2:%{!mips32:-mabi=64}}}}"
+
+#elif MIPS_ABI_DEFAULT == ABI_32
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=32}"
+
+#elif MIPS_ABI_DEFAULT == ABI_N32
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=n32}"
+
+#elif MIPS_ABI_DEFAULT == ABI_64
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=64}"
+
+#elif MIPS_ABI_DEFAULT == ABI_EABI
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=eabi}"
+
+#elif MIPS_ABI_DEFAULT == ABI_O64
+#define ABI_GAS_ASM_SPEC "\
+%{mabi=*} \
+%{!mabi=*:%{mips1|mips2|mips32:-mabi=32} %{!mips1:%{!mips2:%{!mips32:-mabi=o64}}}}"
+
+#elif MIPS_ABI_DEFAULT == ABI_MEABI
+#define ABI_GAS_ASM_SPEC "\
+%{mabi=*} \
+%{!mabi=*:-mabi=meabi }"
+
+#else
+ #error "Unhandled MIPS_ABI_DEFAULT"
+#endif
+
 
 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
    GAS_ASM_SPEC as the default, depending upon the value of
@@ -873,12 +951,11 @@ while (0)
 
 #undef ASM_SPEC
 #define ASM_SPEC "\
-%{!membedded-pic:%{G*}} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
 %(subtarget_asm_optimizing_spec) \
 %(subtarget_asm_debugging_spec) \
 %{membedded-pic} \
-%{mfix7000} \
 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
 %(target_asm_spec) \
 %(subtarget_asm_spec)"
@@ -929,9 +1006,10 @@ while (0)
 #ifndef LINK_SPEC
 #define LINK_SPEC "\
 %(endian_spec) \
-%{G*} %{mips1} %{mips2} %{mips3} %{mips4} \
+%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
 %{bestGnum} %{shared} %{non_shared}"
-#endif	/* LINK_SPEC defined */
+#endif  /* LINK_SPEC defined */
+
 
 /* Specs for the compiler proper */
 
@@ -962,6 +1040,8 @@ while (0)
 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
+%{mips32:-mfp32 -mgp32} \
+%{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
@@ -983,7 +1063,7 @@ while (0)
 
 #ifndef SUBTARGET_CPP_SIZE_SPEC
 #define SUBTARGET_CPP_SIZE_SPEC "\
-%{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
+%{mlong64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}} \
 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
 #endif
 
@@ -1029,6 +1109,8 @@ while (0)
 %(subtarget_cpp_size_spec) \
 %{mips3:-U__mips -D__mips=3 -D__mips64} \
 %{mips4:-U__mips -D__mips=4 -D__mips64} \
+%{mips32:-U__mips -D__mips=32} \
+%{mips64:-U__mips -D__mips=64 -D__mips64} \
 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
 %{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
@@ -1061,6 +1143,7 @@ while (0)
   { "cpp_fpr_spec", CPP_FPR_SPEC },					\
   { "mips_as_asm_spec", MIPS_AS_ASM_SPEC },				\
   { "gas_asm_spec", GAS_ASM_SPEC },					\
+  { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC },                             \
   { "target_asm_spec", TARGET_ASM_SPEC },				\
   { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, 	\
   { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC },	\
@@ -1519,7 +1602,9 @@ do {							\
 
 /* Force right-alignment for small varargs in 32 bit little_endian mode */
 
-#define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
+#define PAD_VARARGS_DOWN (TARGET_64BIT                                  \
+			  || mips_abi == ABI_MEABI                      \
+			     ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
 
 /* Define this macro if an argument declared as `char' or `short' in a
    prototype should actually be passed as an `int'.  In addition to
@@ -1674,10 +1759,7 @@ do {							\
    the R4000 with the FR bit set, the floating point uses register
    pairs, with the second register not being allocable.  */
 
-#define HARD_REGNO_NREGS(REGNO, MODE)					\
-  (! FP_REG_P (REGNO)							\
-	? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
-	: ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
+#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
 
 /* Value is 1 if hard register REGNO can hold a value of machine-mode
    MODE.  In 32 bit mode, require that DImode and DFmode be in even
@@ -2546,6 +2628,7 @@ typedef struct mips_args {
 				/* ??? The size is doubled to work around a
 				   bug in the code that sets the adjustments
 				   in function_arg.  */
+  int prototype;                /* True if the function has a prototype.  */
   struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
 } CUMULATIVE_ARGS;
 
@@ -4411,8 +4494,8 @@ do {									\
 /* Handle certain cpp directives used in header files on sysV.  */
 #define SCCS_DIRECTIVE
 
-#ifndef ASM_OUTPUT_IDENT
 /* Output #ident as a in the read-only data section.  */
+#undef  ASM_OUTPUT_IDENT
 #define ASM_OUTPUT_IDENT(FILE, STRING)					\
 {									\
   const char *p = STRING;						\
@@ -4420,7 +4503,6 @@ do {									\
   rdata_section ();							\
   assemble_string (p, size);						\
 }
-#endif
 
 /* Default to -G 8 */
 #ifndef MIPS_DEFAULT_GVALUE
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 8462162..98ee650 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -30,6 +30,7 @@
 ;; Number	USE
 ;; 0		movsi_ul
 ;; 1		movsi_us, get_fnaddr
+;; 2            reload_in*, reload_out* : sets delay on HILO register
 ;; 3		eh_set_return
 ;; 20		builtin_setjmp_setup
 ;;
@@ -119,7 +120,7 @@
 
 ;; ??? Fix everything that tests this attribute.
 (define_attr "cpu"
-  "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000"
+  "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000,r4kc,r5kc,r20kc"
   (const (symbol_ref "mips_cpu_attr")))
 
 ;; Does the instruction have a mandatory delay slot?
@@ -1711,7 +1712,7 @@
   ""
   "
 {
-  if (HAVE_mulsi3_mult3)
+  if (GENERATE_MULT3_SI || TARGET_MAD)
     emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
   else if (!TARGET_MIPS4000 || TARGET_MIPS16)
     emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
@@ -1727,13 +1728,15 @@
    (clobber (match_scratch:SI 3 "=h,h"))
    (clobber (match_scratch:SI 4 "=l,X"))
    (clobber (match_scratch:SI 5 "=a,a"))]
-  "GENERATE_MULT3
+  "GENERATE_MULT3_SI
    || TARGET_MAD"
   "*
 {
   if (which_alternative == 1)
     return \"mult\\t%1,%2\";
-  if (TARGET_MAD)
+  if (TARGET_MAD
+      || mips_isa == 32
+      || mips_isa == 64)
     return \"mul\\t%0,%1,%2\";
   return \"mult\\t%0,%1,%2\";
 }"
@@ -1796,12 +1799,15 @@
    (clobber (match_scratch:SI 6 "=a,a,a"))
    (clobber (match_scratch:SI 7 "=X,X,d"))]
   "TARGET_MIPS3900
+   || ISA_HAS_MADD_MSUB
    && !TARGET_MIPS16"
   "*
 {
   static const char *const madd[] = { \"madd\\t%1,%2\", \"madd\\t%0,%1,%2\" };
   if (which_alternative == 2)
     return \"#\";
+  if (ISA_HAS_MADD_MSUB && which_alternative != 0)
+    return \"#\";
   return madd[which_alternative];
 }"
   [(set_attr "type"	"imul,imul,multi")
@@ -1827,6 +1833,90 @@
    (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 3)))]
   "")
 
+;; Splitter to copy result of MADD to a general register
+(define_split
+  [(set (match_operand:SI                   0 "register_operand" "")
+        (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
+                          (match_operand:SI 2 "register_operand" ""))
+                 (match_operand:SI          3 "register_operand" "")))
+   (clobber (match_scratch:SI               4 ""))
+   (clobber (match_scratch:SI               5 ""))
+   (clobber (match_scratch:SI               6 ""))
+   (clobber (match_scratch:SI               7 ""))]
+  "reload_completed && GP_REG_P (true_regnum (operands[0]))
+   && true_regnum (operands[3]) == LO_REGNUM"
+  [(parallel [(set (match_dup 3)
+                   (plus:SI (mult:SI (match_dup 1) (match_dup 2))
+                            (match_dup 3)))
+              (clobber (match_dup 4))
+              (clobber (match_dup 5))
+              (clobber (match_dup 6))
+              (clobber (match_dup 7))])
+   (set (match_dup 0) (match_dup 3))]
+  "")
+
+(define_insn "*mul_sub_si"
+  [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
+        (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
+                  (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
+                           (match_operand:SI 3 "register_operand" "d,d,d"))))
+   (clobber (match_scratch:SI 4 "=h,h,h"))
+   (clobber (match_scratch:SI 5 "=X,3,l"))
+   (clobber (match_scratch:SI 6 "=a,a,a"))
+   (clobber (match_scratch:SI 7 "=X,X,d"))]
+  "ISA_HAS_MADD_MSUB"
+  "*
+{
+  if (which_alternative != 0)
+    return \"#\";
+  return \"msub\\t%2,%3\";
+}"
+  [(set_attr "type"     "imul,imul,multi")
+   (set_attr "mode"     "SI")
+   (set_attr "length"   "4,8,8")])
+
+;; Split the above insn if we failed to get LO allocated.
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+        (minus:SI (match_operand:SI 1 "register_operand" "")
+                  (mult:SI (match_operand:SI 2 "register_operand" "")
+                           (match_operand:SI 3 "register_operand" ""))))
+   (clobber (match_scratch:SI 4 ""))
+   (clobber (match_scratch:SI 5 ""))
+   (clobber (match_scratch:SI 6 ""))
+   (clobber (match_scratch:SI 7 ""))]
+  "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[1]))"
+  [(parallel [(set (match_dup 7)
+                   (mult:SI (match_dup 2) (match_dup 3)))
+              (clobber (match_dup 4))
+              (clobber (match_dup 5))
+              (clobber (match_dup 6))])
+   (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 7)))]
+  "")
+
+;; Splitter to copy result of MSUB to a general register
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+        (minus:SI (match_operand:SI 1 "register_operand" "")
+                  (mult:SI (match_operand:SI 2 "register_operand" "")
+                           (match_operand:SI 3 "register_operand" ""))))
+   (clobber (match_scratch:SI 4 ""))
+   (clobber (match_scratch:SI 5 ""))
+   (clobber (match_scratch:SI 6 ""))
+   (clobber (match_scratch:SI 7 ""))]
+  "reload_completed && GP_REG_P (true_regnum (operands[0]))
+   && true_regnum (operands[1]) == LO_REGNUM"
+  [(parallel [(set (match_dup 1)
+                   (minus:SI (match_dup 1)
+                             (mult:SI (match_dup 2) (match_dup 3))))
+              (clobber (match_dup 4))
+              (clobber (match_dup 5))
+              (clobber (match_dup 6))
+              (clobber (match_dup 7))])
+   (set (match_dup 0) (match_dup 1))]
+  "")
+
+
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(minus:SI (match_operand:SI 1 "register_operand" "")
@@ -1855,7 +1945,7 @@
 
   "
 {
-  if (GENERATE_MULT3 || TARGET_MIPS4000 || TARGET_MIPS16)
+  if (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)
     emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
   else
     emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
@@ -1885,10 +1975,10 @@
    (clobber (match_scratch:DI 3 "=h"))
    (clobber (match_scratch:DI 4 "=l"))
    (clobber (match_scratch:DI 5 "=a"))]
-  "TARGET_64BIT && (GENERATE_MULT3 || TARGET_MIPS4000 || TARGET_MIPS16)"
+  "TARGET_64BIT && (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)"
   "*
 {
-  if (GENERATE_MULT3)
+  if (GENERATE_MULT3_DI)
     output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
   else
     {
@@ -1905,7 +1995,7 @@
   [(set_attr "type"	"imul")
    (set_attr "mode"	"DI")
    (set (attr "length")
-	(if_then_else (ne (symbol_ref "GENERATE_MULT3") (const_int 0))
+	(if_then_else (ne (symbol_ref "GENERATE_MULT3_DI") (const_int 0))
 		       (const_int 4)
 		       (const_int 12)))]) 	;; mult + mflo + delay
 
@@ -5086,7 +5176,7 @@ move\\t%0,%z4\\n\\
 	  emit_move_insn (gen_rtx_REG (SImode, 64), scratch);
 	  emit_move_insn (scratch, lo_word);
 	  emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
-          emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
+	  emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
 	}
       else
 	{
@@ -5095,7 +5185,7 @@ move\\t%0,%z4\\n\\
 	  emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
 	  emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
 	  emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
-          emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
+          emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
 	}
       DONE;
     }
@@ -5107,7 +5197,7 @@ move\\t%0,%z4\\n\\
       emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 64)));
       emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
       emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
-      emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
+      emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
       DONE;
     }
   /* This handles moves between a float register and HI/LO.  */
@@ -5137,7 +5227,7 @@ move\\t%0,%z4\\n\\
       emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
       emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
       emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
-      emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
+      emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
       DONE;
     }
   if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
@@ -5166,7 +5256,7 @@ move\\t%0,%z4\\n\\
 	  emit_move_insn (hi_word, scratch);
 	  emit_move_insn (scratch, gen_rtx_REG (SImode, 65));
 	  emit_move_insn (lo_word, scratch);
-	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
+	  emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
 	}
       else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0])))
 	{
@@ -5181,7 +5271,7 @@ move\\t%0,%z4\\n\\
 	  emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32)));
 	  emit_insn (gen_iordi3 (scratch, scratch, scratch2));
 	  emit_insn (gen_movdi (operands[0], scratch));
-	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
+	  emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
 	}
       else
 	{
@@ -5191,7 +5281,7 @@ move\\t%0,%z4\\n\\
 	  emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
 	  emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
 	  emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
-	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
+	  emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
 	}
       DONE;
     }
@@ -5517,7 +5607,7 @@ move\\t%0,%z4\\n\\
       emit_insn (gen_movsi (gen_rtx_REG (SImode, 65), operands[1]));
       emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
       emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
-      emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
+      emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
       DONE;
     }
   /* Use a mult to reload LO on mips16.  ??? This is hideous.  */
@@ -5642,6 +5732,15 @@ move\\t%0,%z4\\n\\
   DONE;
 }")
 
+;; This insn is for the unspec delay for HILO.
+
+(define_insn "*HILO_delay"
+  [(unspec [(match_operand 0 "register_operand" "=b")] 2 )]
+  ""
+  ""
+  [(set_attr "type" "nop")
+   (set_attr "mode" "none")])
+
 ;; This insn handles moving CCmode values.  It's really just a
 ;; slightly simplified copy of movsi_internal2, with additional cases
 ;; to move a condition register to a general register and to move
@@ -10339,6 +10438,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
   "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
   "
 {
+  if (mips_isa == 32)
+    FAIL;
   gen_conditional_move (operands);
   DONE;
 }")
diff --git a/gcc/config/mips/t-isa3264 b/gcc/config/mips/t-isa3264
new file mode 100644
index 0000000..22afb21
--- /dev/null
+++ b/gcc/config/mips/t-isa3264
@@ -0,0 +1,103 @@
+CONFIG2_H	= $(srcdir)/config/mips/isa3264.h $(srcdir)/config/mips/elf.h $(srcdir)/config/mips/ecoff.h $(srcdir)/config/mips/mips.h
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# When building a cross compiler, put the mips16 support functions in
+# libgcc1.a.
+CROSS_LIBGCC1 = libgcc1-asm.a
+LIB1ASMSRC = mips/mips16.S
+LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
+	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
+	_m16fltsisf _m16fixsfsi \
+	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
+	_m16extsfdf2 _m16trdfsf2 \
+	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
+	_m16fltsidf _m16fixdfsi \
+	_m16retsf _m16retdf \
+	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
+	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
+	_m16stubsf9 _m16stubsf10 \
+	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
+	_m16stubdf9 _m16stubdf10
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# fp-bit and dp-bit are really part of libgcc1, but this will cause
+# them to be built correctly, so... [taken from t-sparclite]
+# We want fine grained libraries, so use the new code to build the
+# floating point emulation libraries.
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __MIPSEL__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
+	echo '#endif' >> dp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __MIPSEL__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
+	echo '#endif' >> fp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = msoft-float EL/EB mips32/mips64
+MULTILIB_DIRNAMES = soft-float el eb mips32 mips64
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# Add additional dependencies to recompile selected modules whenever the
+# tm.h file changes.  The files compiled are:
+#
+#	gcc.c		(*_SPEC changes)
+#	toplev.c	(new switches + assembly output changes)
+#	sdbout.c	(debug format changes)
+#	dbxout.c	(debug format changes)
+#	dwarfout.c	(debug format changes)
+#	final.c		(assembly output changes)
+#	varasm.c	(assembly output changes)
+#	cse.c		(cost functions)
+#	insn-output.c	(possible ifdef changes in tm.h)
+#	regclass.c	(fixed/call used register changes)
+#	cccp.c		(new preprocessor macros, -v version #)
+#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
+#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
+#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
+
+gcc.o: $(CONFIG2_H)
+toplev.o: $(CONFIG2_H)
+sdbout.o: $(CONFIG2_H)
+dbxout.o: $(CONFIG2_H)
+dwarfout.o: $(CONFIG2_H)
+final.o: $(CONFIG2_H)
+varasm.o: $(CONFIG2_H)
+cse.o: $(CONFIG2_H)
+insn-output.o: $(CONFIG2_H)
+regclass.o: $(CONFIG2_H)
+cccp.o: $(CONFIG2_H)
+explow.o: $(CONFIG2_H)
+recog.o: $(CONFIG2_H)
+reload.o: $(CONFIG2_H)