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| author | Vladimir Makarov <vmakarov@redhat.com> | 2015-11-27 18:26:12 +0000 |
|---|---|---|
| committer | Vladimir Makarov <vmakarov@gcc.gnu.org> | 2015-11-27 18:26:12 +0000 |
| commit | 0b87be09b012920618fa78ac4cef269e02614924 (patch) | |
| tree | bbdcf30112b4d67b3294abd65a3dd7d217763fd2 | |
| parent | 921da19854e9f9dba416dc68c57379231c6ca52b (diff) | |
| download | gcc-0b87be09b012920618fa78ac4cef269e02614924.zip gcc-0b87be09b012920618fa78ac4cef269e02614924.tar.gz gcc-0b87be09b012920618fa78ac4cef269e02614924.tar.bz2 | |
re PR rtl-optimization/68536 (LRA ICEs with new arm pattern)
2015-11-27 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/68536
* lra.c (lra_emit_add): Add code for null base.
* lra-constraints.c (curr_insn_transform): Skip operators for
subreg reloads.
From-SVN: r231021
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/lra-constraints.c | 7 | ||||
| -rw-r--r-- | gcc/lra.c | 20 |
3 files changed, 27 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fb51999..b30e9a1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-11-27 Vladimir Makarov <vmakarov@redhat.com> + + PR rtl-optimization/68536 + * lra.c (lra_emit_add): Add code for null base. + * lra-constraints.c (curr_insn_transform): Skip operators for + subreg reloads. + 2015-11-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Revert diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index f2d5b40..a78edd8 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -3383,10 +3383,13 @@ curr_insn_transform (bool check_only_p) depend on memory mode. */ for (i = 0; i < n_operands; i++) { - rtx op = *curr_id->operand_loc[i]; - rtx subst, old = op; + rtx op, subst, old; bool op_change_p = false; + + if (curr_static_id->operand[i].is_operator) + continue; + old = op = *curr_id->operand_loc[i]; if (GET_CODE (old) == SUBREG) old = SUBREG_REG (old); subst = get_equiv_with_elimination (old, curr_insn); @@ -382,7 +382,7 @@ lra_emit_add (rtx x, rtx y, rtx z) base = a1; index = a2; } - if (! (REG_P (base) || GET_CODE (base) == SUBREG) + if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG)) || (index != NULL_RTX && ! (REG_P (index) || GET_CODE (index) == SUBREG)) || (disp != NULL_RTX && ! CONSTANT_P (disp)) @@ -442,18 +442,28 @@ lra_emit_add (rtx x, rtx y, rtx z) rtx_insn *insn = emit_add2_insn (x, disp); if (insn != NULL_RTX) { - insn = emit_add2_insn (x, base); - if (insn != NULL_RTX) + if (base == NULL_RTX) ok_p = true; + else + { + insn = emit_add2_insn (x, base); + if (insn != NULL_RTX) + ok_p = true; + } } } if (! ok_p) { + rtx_insn *insn; + delete_insns_since (last); /* Generate x = disp; x = x + base; x = x + index_scale. */ emit_move_insn (x, disp); - rtx_insn *insn = emit_add2_insn (x, base); - lra_assert (insn != NULL_RTX); + if (base != NULL_RTX) + { + insn = emit_add2_insn (x, base); + lra_assert (insn != NULL_RTX); + } insn = emit_add2_insn (x, index_scale); lra_assert (insn != NULL_RTX); } |