i386.md (fyl2xxf3_i387): Rename from fyl2x_xf3.

	* config/i386/i386.md (fyl2xxf3_i387): Rename from fyl2x_xf3.
	(fyl2x_extend<mode>xf3_i387): New insn pattern.
	(log<mode>2): Rename from logsf2 and logdf2 and macroize insn
	insn patterns using X87MODEF12 mode macro.  Extend operand 1
	to XFmode. Use SSE_FLOAT_MODE_P to disable patterns for SSE math.
	(log10<mode>2): Ditto.
	(log2<mode>2): Ditto.
	(log1p<mode>2): Ditto.
	(logb<mode>2): Ditto.
	(fyl2xp1xf3_i387): Rename from fyl2xp1_xf3.
	(fyl2xp1_extend<mode>xf3_i387): New insn pattern.
	(*fxtractxf3_i387): Rename from *fxtractxf3.
	(fxtract_extend<mode>xf3_i387): New insn pattern.
	(ilogbsi2): Use match_dup 3, not match_operand:XF 3.

	* config/i386/i386.c (ix86_emit_i387_log1p): Use gen_fyl2xp1xf3_i387()
	and gen_fyl2xxf3_i387().

From-SVN: r120792

3 files changed, 139 insertions, 193 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 24d6dc6..820c45c5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,23 @@
+2007-01-15  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (fyl2xxf3_i387): Rename from fyl2x_xf3.
+	(fyl2x_extend<mode>xf3_i387): New insn pattern.
+	(log<mode>2): Rename from logsf2 and logdf2 and macroize insn
+	insn patterns using X87MODEF12 mode macro.  Extend operand 1
+	to XFmode. Use SSE_FLOAT_MODE_P to disable patterns for SSE math.
+	(log10<mode>2): Ditto.
+	(log2<mode>2): Ditto.
+	(log1p<mode>2): Ditto.
+	(logb<mode>2): Ditto.
+	(fyl2xp1xf3_i387): Rename from fyl2xp1_xf3.
+	(fyl2xp1_extend<mode>xf3_i387): New insn pattern.
+	(*fxtractxf3_i387): Rename from *fxtractxf3.
+	(fxtract_extend<mode>xf3_i387): New insn pattern.
+	(ilogbsi2): Use match_dup 3, not match_operand:XF 3.
+
+	* config/i386/i386.c (ix86_emit_i387_log1p): Use gen_fyl2xp1xf3_i387()
+	and gen_fyl2xxf3_i387().
+
 2007-01-14  Zdenek Dvorak <dvorakz@suse.cz>
 
 	* loop-unswitch.c (unswitch_loop): Do not call fix_loop_placement.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a2ec4d8..123c817 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -20143,14 +20143,14 @@ void ix86_emit_i387_log1p (rtx op0, rtx op1)
   emit_jump_insn (gen_bge (label1));
 
   emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
-  emit_insn (gen_fyl2xp1_xf3 (op0, tmp2, op1));
+  emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
   emit_jump (label2);
 
   emit_label (label1);
   emit_move_insn (tmp, CONST1_RTX (XFmode));
   emit_insn (gen_addxf3 (tmp, op1, tmp));
   emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
-  emit_insn (gen_fyl2x_xf3 (op0, tmp2, tmp));
+  emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
 
   emit_label (label2);
 }
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index fa8ac3b..c4567f6 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -16255,65 +16255,64 @@
   emit_move_insn (operands[3], CONST1_RTX (XFmode));  /* fld1 */
 })
 
-(define_insn "fyl2x_xf3"
+(define_insn "fyl2xxf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
-        (unspec:XF [(match_operand:XF 2 "register_operand" "0")
-		    (match_operand:XF 1 "register_operand" "u")]
+        (unspec:XF [(match_operand:XF 1 "register_operand" "0")
+		    (match_operand:XF 2 "register_operand" "u")]
 	           UNSPEC_FYL2X))
-   (clobber (match_scratch:XF 3 "=1"))]
+   (clobber (match_scratch:XF 3 "=2"))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
   "fyl2x"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
-(define_expand "logsf2"
-  [(set (match_dup 2)
-	(float_extend:XF (match_operand:SF 1 "register_operand" "")))
-   (parallel [(set (match_dup 4)
-		   (unspec:XF [(match_dup 2)
-			       (match_dup 3)] UNSPEC_FYL2X))
-	      (clobber (match_scratch:XF 5 ""))])
-   (set (match_operand:SF 0 "register_operand" "")
-	(float_truncate:SF (match_dup 4)))]
+(define_insn "fyl2x_extend<mode>xf3_i387"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+        (unspec:XF [(float_extend:XF
+		      (match_operand:X87MODEF 1 "register_operand" "0"))
+		    (match_operand:XF 2 "register_operand" "u")]
+	           UNSPEC_FYL2X))
+   (clobber (match_scratch:XF 3 "=2"))]
   "TARGET_USE_FANCY_MATH_387
-   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
+   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+       || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
-{
-  rtx temp;
+  "fyl2x"
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "XF")])
 
+(define_expand "logxf2"
+  [(parallel [(set (match_operand:XF 0 "register_operand" "")
+		   (unspec:XF [(match_operand:XF 1 "register_operand" "")
+			       (match_dup 2)] UNSPEC_FYL2X))
+	      (clobber (match_scratch:XF 3 ""))])]
+  "TARGET_USE_FANCY_MATH_387
+   && flag_unsafe_math_optimizations"
+{
   operands[2] = gen_reg_rtx (XFmode);
-  operands[3] = gen_reg_rtx (XFmode);
-  operands[4] = gen_reg_rtx (XFmode);
-
-  temp = standard_80387_constant_rtx (4); /* fldln2 */
-  emit_move_insn (operands[3], temp);
+  emit_move_insn (operands[2], standard_80387_constant_rtx (4)); /* fldln2 */
 })
 
-(define_expand "logdf2"
-  [(set (match_dup 2)
-	(float_extend:XF (match_operand:DF 1 "register_operand" "")))
-   (parallel [(set (match_dup 4)
-		   (unspec:XF [(match_dup 2)
-			       (match_dup 3)] UNSPEC_FYL2X))
-	      (clobber (match_scratch:XF 5 ""))])
-   (set (match_operand:DF 0 "register_operand" "")
-	(float_truncate:DF (match_dup 4)))]
+(define_expand "log<mode>2"
+  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
-   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
+   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+       || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx temp;
+  rtx op0 = gen_reg_rtx (XFmode);
 
   operands[2] = gen_reg_rtx (XFmode);
-  operands[3] = gen_reg_rtx (XFmode);
-  operands[4] = gen_reg_rtx (XFmode);
+  emit_move_insn (operands[2], standard_80387_constant_rtx (4)); /* fldln2 */
 
-  temp = standard_80387_constant_rtx (4); /* fldln2 */
-  emit_move_insn (operands[3], temp);
+  emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], operands[2]));
+  emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
+  DONE;
 })
 
-(define_expand "logxf2"
+(define_expand "log10xf2"
   [(parallel [(set (match_operand:XF 0 "register_operand" "")
 		   (unspec:XF [(match_operand:XF 1 "register_operand" "")
 			       (match_dup 2)] UNSPEC_FYL2X))
@@ -16321,60 +16320,29 @@
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
 {
-  rtx temp;
-
   operands[2] = gen_reg_rtx (XFmode);
-  temp = standard_80387_constant_rtx (4); /* fldln2 */
-  emit_move_insn (operands[2], temp);
+  emit_move_insn (operands[2], standard_80387_constant_rtx (3)); /* fldlg2 */
 })
 
-(define_expand "log10sf2"
-  [(set (match_dup 2)
-	(float_extend:XF (match_operand:SF 1 "register_operand" "")))
-   (parallel [(set (match_dup 4)
-		   (unspec:XF [(match_dup 2)
-			       (match_dup 3)] UNSPEC_FYL2X))
-	      (clobber (match_scratch:XF 5 ""))])
-   (set (match_operand:SF 0 "register_operand" "")
-	(float_truncate:SF (match_dup 4)))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-{
-  rtx temp;
-
-  operands[2] = gen_reg_rtx (XFmode);
-  operands[3] = gen_reg_rtx (XFmode);
-  operands[4] = gen_reg_rtx (XFmode);
-
-  temp = standard_80387_constant_rtx (3); /* fldlg2 */
-  emit_move_insn (operands[3], temp);
-})
-
-(define_expand "log10df2"
-  [(set (match_dup 2)
-	(float_extend:XF (match_operand:DF 1 "register_operand" "")))
-   (parallel [(set (match_dup 4)
-		   (unspec:XF [(match_dup 2)
-			       (match_dup 3)] UNSPEC_FYL2X))
-	      (clobber (match_scratch:XF 5 ""))])
-   (set (match_operand:DF 0 "register_operand" "")
-	(float_truncate:DF (match_dup 4)))]
+(define_expand "log10<mode>2"
+  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
-   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
+   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+       || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  rtx temp;
+  rtx op0 = gen_reg_rtx (XFmode);
 
   operands[2] = gen_reg_rtx (XFmode);
-  operands[3] = gen_reg_rtx (XFmode);
-  operands[4] = gen_reg_rtx (XFmode);
+  emit_move_insn (operands[2], standard_80387_constant_rtx (3)); /* fldlg2 */
 
-  temp = standard_80387_constant_rtx (3); /* fldlg2 */
-  emit_move_insn (operands[3], temp);
+  emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], operands[2]));
+  emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
+  DONE;
 })
 
-(define_expand "log10xf2"
+(define_expand "log2xf2"
   [(parallel [(set (match_operand:XF 0 "register_operand" "")
 		   (unspec:XF [(match_operand:XF 1 "register_operand" "")
 			       (match_dup 2)] UNSPEC_FYL2X))
@@ -16382,120 +16350,83 @@
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
 {
-  rtx temp;
-
   operands[2] = gen_reg_rtx (XFmode);
-  temp = standard_80387_constant_rtx (3); /* fldlg2 */
-  emit_move_insn (operands[2], temp);
+  emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
 })
 
-(define_expand "log2sf2"
-  [(set (match_dup 2)
-	(float_extend:XF (match_operand:SF 1 "register_operand" "")))
-   (parallel [(set (match_dup 4)
-		   (unspec:XF [(match_dup 2)
-			       (match_dup 3)] UNSPEC_FYL2X))
-	      (clobber (match_scratch:XF 5 ""))])
-   (set (match_operand:SF 0 "register_operand" "")
-	(float_truncate:SF (match_dup 4)))]
+(define_expand "log2<mode>2"
+  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
-   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
+   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+       || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
-  operands[2] = gen_reg_rtx (XFmode);
-  operands[3] = gen_reg_rtx (XFmode);
-  operands[4] = gen_reg_rtx (XFmode);
-
-  emit_move_insn (operands[3], CONST1_RTX (XFmode));  /* fld1 */
-})
+  rtx op0 = gen_reg_rtx (XFmode);
 
-(define_expand "log2df2"
-  [(set (match_dup 2)
-	(float_extend:XF (match_operand:DF 1 "register_operand" "")))
-   (parallel [(set (match_dup 4)
-		   (unspec:XF [(match_dup 2)
-			       (match_dup 3)] UNSPEC_FYL2X))
-	      (clobber (match_scratch:XF 5 ""))])
-   (set (match_operand:DF 0 "register_operand" "")
-	(float_truncate:DF (match_dup 4)))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-{
   operands[2] = gen_reg_rtx (XFmode);
-  operands[3] = gen_reg_rtx (XFmode);
-  operands[4] = gen_reg_rtx (XFmode);
+  emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
 
-  emit_move_insn (operands[3], CONST1_RTX (XFmode));  /* fld1 */
+  emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], operands[2]));
+  emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
+  DONE;
 })
 
-(define_expand "log2xf2"
-  [(parallel [(set (match_operand:XF 0 "register_operand" "")
-		   (unspec:XF [(match_operand:XF 1 "register_operand" "")
-			       (match_dup 2)] UNSPEC_FYL2X))
-	      (clobber (match_scratch:XF 3 ""))])]
+(define_insn "fyl2xp1xf3_i387"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+        (unspec:XF [(match_operand:XF 1 "register_operand" "0")
+		    (match_operand:XF 2 "register_operand" "u")]
+	           UNSPEC_FYL2XP1))
+   (clobber (match_scratch:XF 3 "=2"))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
-{
-  operands[2] = gen_reg_rtx (XFmode);
-  emit_move_insn (operands[2], CONST1_RTX (XFmode));  /* fld1 */
-})
+  "fyl2xp1"
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "XF")])
 
-(define_insn "fyl2xp1_xf3"
+(define_insn "fyl2xp1_extend<mode>xf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
-        (unspec:XF [(match_operand:XF 2 "register_operand" "0")
-		    (match_operand:XF 1 "register_operand" "u")]
+        (unspec:XF [(float_extend:XF
+		      (match_operand:X87MODEF12 1 "register_operand" "0"))
+		    (match_operand:XF 2 "register_operand" "u")]
 	           UNSPEC_FYL2XP1))
-   (clobber (match_scratch:XF 3 "=1"))]
+   (clobber (match_scratch:XF 3 "=2"))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+       || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fyl2xp1"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
-(define_expand "log1psf2"
-  [(use (match_operand:SF 0 "register_operand" ""))
-   (use (match_operand:SF 1 "register_operand" ""))]
+(define_expand "log1pxf2"
+  [(use (match_operand:XF 0 "register_operand" ""))
+   (use (match_operand:XF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
-   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations && !optimize_size"
 {
-  rtx op0 = gen_reg_rtx (XFmode);
-  rtx op1 = gen_reg_rtx (XFmode);
-
-  emit_insn (gen_extendsfxf2 (op1, operands[1]));
-  ix86_emit_i387_log1p (op0, op1);
-  emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
+  ix86_emit_i387_log1p (operands[0], operands[1]);
   DONE;
 })
 
-(define_expand "log1pdf2"
-  [(use (match_operand:DF 0 "register_operand" ""))
-   (use (match_operand:DF 1 "register_operand" ""))]
+(define_expand "log1p<mode>2"
+  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
-   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
+   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+       || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations && !optimize_size"
 {
   rtx op0 = gen_reg_rtx (XFmode);
-  rtx op1 = gen_reg_rtx (XFmode);
 
-  emit_insn (gen_extenddfxf2 (op1, operands[1]));
-  ix86_emit_i387_log1p (op0, op1);
-  emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
-  DONE;
-})
+  operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]);
 
-(define_expand "log1pxf2"
-  [(use (match_operand:XF 0 "register_operand" ""))
-   (use (match_operand:XF 1 "register_operand" ""))]
-  "TARGET_USE_FANCY_MATH_387
-   && flag_unsafe_math_optimizations && !optimize_size"
-{
-  ix86_emit_i387_log1p (operands[0], operands[1]);
+  ix86_emit_i387_log1p (op0, operands[1]);
+  emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
   DONE;
 })
 
-(define_insn "*fxtractxf3"
+(define_insn "*fxtractxf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(unspec:XF [(match_operand:XF 2 "register_operand" "0")]
 		   UNSPEC_XTRACT_FRACT))
@@ -16507,41 +16438,20 @@
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
-(define_expand "logbsf2"
-  [(set (match_dup 2)
-	(float_extend:XF (match_operand:SF 1 "register_operand" "")))
-   (parallel [(set (match_dup 3)
-		   (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
-	      (set (match_dup 4)
-		   (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
-   (set (match_operand:SF 0 "register_operand" "")
-	(float_truncate:SF (match_dup 4)))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-{
-  operands[2] = gen_reg_rtx (XFmode);
-  operands[3] = gen_reg_rtx (XFmode);
-  operands[4] = gen_reg_rtx (XFmode);
-})
-
-(define_expand "logbdf2"
-  [(set (match_dup 2)
-	(float_extend:XF (match_operand:DF 1 "register_operand" "")))
-   (parallel [(set (match_dup 3)
-		   (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
-	      (set (match_dup 4)
-		   (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
-   (set (match_operand:DF 0 "register_operand" "")
-	(float_truncate:DF (match_dup 4)))]
+(define_insn "fxtract_extend<mode>xf3_i387"
+  [(set (match_operand:XF 0 "register_operand" "=f")
+	(unspec:XF [(float_extend:XF
+		      (match_operand:X87MODEF12 2 "register_operand" "0"))]
+		   UNSPEC_XTRACT_FRACT))
+   (set (match_operand:XF 1 "register_operand" "=u")
+        (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_XTRACT_EXP))]
   "TARGET_USE_FANCY_MATH_387
-   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
+   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+       || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
-{
-  operands[2] = gen_reg_rtx (XFmode);
-  operands[3] = gen_reg_rtx (XFmode);
-  operands[4] = gen_reg_rtx (XFmode);
-})
+  "fxtract"
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "XF")])
 
 (define_expand "logbxf2"
   [(parallel [(set (match_dup 2)
@@ -16555,11 +16465,27 @@
   operands[2] = gen_reg_rtx (XFmode);
 })
 
+(define_expand "logb<mode>2"
+  [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+   (use (match_operand:X87MODEF12 1 "register_operand" ""))]
+  "TARGET_USE_FANCY_MATH_387
+   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+       || TARGET_MIX_SSE_I387)
+   && flag_unsafe_math_optimizations"
+{
+  rtx op0 = gen_reg_rtx (XFmode);
+  rtx op1 = gen_reg_rtx (XFmode);
+
+  emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
+  emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op1));
+  DONE;
+})
+
 (define_expand "ilogbsi2"
   [(parallel [(set (match_dup 2)
 		   (unspec:XF [(match_operand:XF 1 "register_operand" "")]
 			      UNSPEC_XTRACT_FRACT))
-	      (set (match_operand:XF 3 "register_operand" "")
+	      (set (match_dup 3)
 		   (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])
    (parallel [(set (match_operand:SI 0 "register_operand" "")
 	           (fix:SI (match_dup 3)))