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authorGanesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>2013-05-13 09:35:54 +0000
committerGanesh Gopalasubramanian <gganesh@gcc.gnu.org>2013-05-13 09:35:54 +0000
commit0864bfc257a3d3198ba182c562b729ba1e96466d (patch)
tree7d3180704c8685e4b78739287684635c81f15644
parent640bfeb25ce9b2f645c75d1e04ecce9ad74c4be1 (diff)
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AMD specific default alignment changes
From-SVN: r198820
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/i386/i386.c10
2 files changed, 10 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 945f525..b33e4f3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-05-13 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ * config/i386/i386.c (processor_target_table): Modified default
+ alignment values for AMD BD and BT architectures.
+
2013-05-13 Marc Glisse <marc.glisse@inria.fr>
* tree-vect-generic.c (uniform_vector_p): Move ...
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 86439ba..c28a857 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2453,11 +2453,11 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
{&generic32_cost, 16, 7, 16, 7, 16},
{&generic64_cost, 16, 10, 16, 10, 16},
{&amdfam10_cost, 32, 24, 32, 7, 32},
- {&bdver1_cost, 32, 24, 32, 7, 32},
- {&bdver2_cost, 32, 24, 32, 7, 32},
- {&bdver3_cost, 32, 24, 32, 7, 32},
- {&btver1_cost, 32, 24, 32, 7, 32},
- {&btver2_cost, 32, 24, 32, 7, 32},
+ {&bdver1_cost, 16, 10, 16, 7, 11},
+ {&bdver2_cost, 16, 10, 16, 7, 11},
+ {&bdver3_cost, 16, 10, 16, 7, 11},
+ {&btver1_cost, 16, 10, 16, 7, 11},
+ {&btver2_cost, 16, 10, 16, 7, 11},
{&atom_cost, 16, 15, 16, 7, 16}
};