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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:20:28 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:20:28 -0700 |
| commit | 018a45bdf3e3cbed5fbdd6db19457c63fea5f7bf (patch) | |
| tree | e79f04c346f7117f55997b8ebfd7383be285c18a | |
| parent | d9d6e621ff522a0bdcfac90f8e9bda1a8b9f4577 (diff) | |
| download | gcc-018a45bdf3e3cbed5fbdd6db19457c63fea5f7bf.zip gcc-018a45bdf3e3cbed5fbdd6db19457c63fea5f7bf.tar.gz gcc-018a45bdf3e3cbed5fbdd6db19457c63fea5f7bf.tar.bz2 | |
i386: Emulate MMX mmx_psadbw with SSE
Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.
From-SVN: r271237
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 19 |
2 files changed, 17 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eefdecd..84cf0aa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,11 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_psadbw): Add SSE emulation. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv4hi3): Add SSE emulation. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 338f77e..15fd355 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1796,14 +1796,19 @@ (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_psadbw" - [(set (match_operand:V1DI 0 "register_operand" "=y") - (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")] + [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv") + (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0,0,Yv") + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")] UNSPEC_PSADBW))] - "TARGET_SSE || TARGET_3DNOW_A" - "psadbw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "@ + psadbw\t{%2, %0|%0, %2} + psadbw\t{%2, %0|%0, %2} + vpsadbw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_insn_and_split "mmx_pmovmskb" [(set (match_operand:SI 0 "register_operand" "=r,r") |