c.opt: Add -flax-vector-conversions.

	gcc/
	* c.opt: Add -flax-vector-conversions.
	* c-typeck.c (convert_for_assignment): Pass flag to
	vector_types_convertible_p to allow emission of note.
	(digest_init): Likewise.
	(comptypes_internal): Use vector_types_convertible_p.
	* c-opts.c: Handle -flax-vector-conversions.
	* c-common.c (flag_lax_vector_conversions): New.
	(vector_types_convertible_p): Unless -flax-vector conversions
	has been passed, disallow conversions between vectors with
	differing numbers of subparts and/or element types.  If such
	a conversion is disallowed, possibly emit a note on the first
	occasion only to inform the user of -flax-vector-conversions.
	The new last argument specifies this.
	* c-common.h (flag_lax_vector_conversions): New.
	(vector_types_convertible_p): Add extra argument.
	* config/i386/i386.c (ix86_init_mmx_sse_builtins): Use
	char_type_node for V*QI type vectors.
	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins):
	Update to satisfy new typechecking rules.
	* config/rs6000/altivec.h (vec_cmple): Use vec_cmpge.
	* doc/invoke.texi (C Dialect Options): Document
	-flax-vector-conversions.

	gcc/cp/
	* call.c (standard_conversion): Pass flag to
	vector_types_convertible_p to disallow emission of note.
	* typeck.c (convert_for_assignment): Pass flag to
	vector_types_convertible_p to allow emission of note.
	(ptr_reasonably_similar): Pass flag to vector_types_convertible_p
	to disallow emission of note.

	gcc/testsuite/
	* gcc.target/i386/20020531-1.c: Use "char" not "unsigned char"
	in __v8qi typedef.
	* gcc.target/powerpc/altivec-vec-merge.c (foo): Add casts.
	* gcc.dg/simd-1.c: Update dg-error directives to reflect new
	compiler behaviour.
	* gcc.dg/simd-5.c: Likewise.
	* gcc.dg/simd-6.c: Likewise.
	* g++.dg/conversion/simd1.C: Likewise.
	* g++.dg/conversion/simd3.C: Likewise.
	* g++.dg/ext/attribute-test-2.C (data): Add "vs" member.
	(main): Use it.

From-SVN: r120572

22 files changed, 150 insertions, 66 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 371f105..c5b803b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,30 @@
 2007-01-08  Mark Shinwell  <shinwell@codesourcery.com>
 
+	* c.opt: Add -flax-vector-conversions.
+	* c-typeck.c (convert_for_assignment): Pass flag to
+	vector_types_convertible_p to allow emission of note.
+	(digest_init): Likewise.
+	* c-opts.c: Handle -flax-vector-conversions.
+	* c-common.c (flag_lax_vector_conversions): New.
+	(vector_types_convertible_p): Unless -flax-vector conversions
+	has been passed, disallow conversions between vectors with
+	differing numbers of subparts and/or element types.  If such
+	a conversion is disallowed, possibly emit a note on the first
+	occasion only to inform the user of -flax-vector-conversions.
+	The new last argument specifies this.
+	* c-common.h (flag_lax_vector_conversions): New.
+	(vector_types_convertible_p): Add extra argument.
+	* config/i386/i386.c (ix86_init_mmx_sse_builtins): Use
+	char_type_node for V*QI type vectors.
+	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins):
+	Update to satisfy new typechecking rules.
+	* config/rs6000/altivec.h (vec_cmple): Use vec_cmpge, for both
+	C and C++ variants.
+	* doc/invoke.texi (C Dialect Options): Document
+	-flax-vector-conversions.
+
+2007-01-08  Mark Shinwell  <shinwell@codesourcery.com>
+
 	PR tree-optimization/29877
 	* tree-ssa-ter.c (is_replaceable_p): Deem assignments with
 	a register variable on the RHS to not be replaceable.
diff --git a/gcc/c-common.c b/gcc/c-common.c
index 8fb9541..ef4c2e8 100644
--- a/gcc/c-common.c
+++ b/gcc/c-common.c
@@ -254,6 +254,10 @@ int flag_short_double;
 
 int flag_short_wchar;
 
+/* Nonzero means allow implicit conversions between vectors with
+   differing numbers of subparts and/or differing element types.  */
+int flag_lax_vector_conversions;
+
 /* Nonzero means allow Microsoft extensions without warnings or errors.  */
 int flag_ms_extensions;
 
@@ -1078,19 +1082,40 @@ check_main_parameter_types (tree decl)
    pedwarn ("%q+D takes only zero or two arguments", decl);
 }
 
- 
-/* Nonzero if vector types T1 and T2 can be converted to each other
-   without an explicit cast.  */
-int
-vector_types_convertible_p (tree t1, tree t2)
-{
-  return targetm.vector_opaque_p (t1)
-	 || targetm.vector_opaque_p (t2)
-	 || (tree_int_cst_equal (TYPE_SIZE (t1), TYPE_SIZE (t2))
-	     && (TREE_CODE (TREE_TYPE (t1)) != REAL_TYPE ||
-		 TYPE_PRECISION (t1) == TYPE_PRECISION (t2))
-	     && INTEGRAL_TYPE_P (TREE_TYPE (t1))
-		== INTEGRAL_TYPE_P (TREE_TYPE (t2)));
+/* True if vector types T1 and T2 can be converted to each other
+   without an explicit cast.  If EMIT_LAX_NOTE is true, and T1 and T2
+   can only be converted with -flax-vector-conversions yet that is not
+   in effect, emit a note telling the user about that option if such
+   a note has not previously been emitted.  */
+bool
+vector_types_convertible_p (tree t1, tree t2, bool emit_lax_note)
+{
+  static bool emitted_lax_note = false;
+  bool convertible_lax =
+    targetm.vector_opaque_p (t1)
+    || targetm.vector_opaque_p (t2)
+    || (tree_int_cst_equal (TYPE_SIZE (t1), TYPE_SIZE (t2))
+        && (TREE_CODE (TREE_TYPE (t1)) != REAL_TYPE ||
+           TYPE_PRECISION (t1) == TYPE_PRECISION (t2))
+       && INTEGRAL_TYPE_P (TREE_TYPE (t1))
+          == INTEGRAL_TYPE_P (TREE_TYPE (t2)));
+
+  if (!convertible_lax || flag_lax_vector_conversions)
+    return convertible_lax;
+
+  if (TYPE_VECTOR_SUBPARTS (t1) == TYPE_VECTOR_SUBPARTS (t2)
+      && comptypes (TREE_TYPE (t1), TREE_TYPE (t2)))
+    return true;
+
+  if (emit_lax_note && !emitted_lax_note)
+    {
+      emitted_lax_note = true;
+      inform ("use -flax-vector-conversions to permit "
+              "conversions between vectors with differing "
+              "element types or numbers of subparts");
+    }
+
+  return false;
 }
 
 /* Warns if the conversion of EXPR to TYPE may alter a value.
diff --git a/gcc/c-common.h b/gcc/c-common.h
index 86b4487..7b35256 100644
--- a/gcc/c-common.h
+++ b/gcc/c-common.h
@@ -392,6 +392,10 @@ extern int flag_short_double;
 
 extern int flag_short_wchar;
 
+/* Nonzero means allow implicit conversions between vectors with
+   differing numbers of subparts and/or differing element types.  */
+extern int flag_lax_vector_conversions;
+
 /* Nonzero means allow Microsoft extensions without warnings or errors.  */
 extern int flag_ms_extensions;
 
@@ -801,7 +805,7 @@ extern tree finish_label_address_expr (tree);
 extern tree lookup_label (tree);
 extern tree lookup_name (tree);
 
-extern int vector_types_convertible_p (tree t1, tree t2);
+extern bool vector_types_convertible_p (tree t1, tree t2, bool emit_lax_note);
 
 extern rtx c_expand_expr (tree, rtx, enum machine_mode, int, rtx *);
 
diff --git a/gcc/c-opts.c b/gcc/c-opts.c
index acba12b..67adab8 100644
--- a/gcc/c-opts.c
+++ b/gcc/c-opts.c
@@ -705,6 +705,10 @@ c_common_handle_option (size_t scode, const char *arg, int value)
       flag_implicit_templates = value;
       break;
 
+    case OPT_flax_vector_conversions:
+      flag_lax_vector_conversions = value;
+      break;
+
     case OPT_fms_extensions:
       flag_ms_extensions = value;
       break;
diff --git a/gcc/c-typeck.c b/gcc/c-typeck.c
index 8119e7f..50db7d4 100644
--- a/gcc/c-typeck.c
+++ b/gcc/c-typeck.c
@@ -3873,7 +3873,7 @@ convert_for_assignment (tree type, tree rhs, enum impl_conv errtype,
     }
   /* Some types can interconvert without explicit casts.  */
   else if (codel == VECTOR_TYPE && coder == VECTOR_TYPE
-	   && vector_types_convertible_p (type, TREE_TYPE (rhs)))
+	   && vector_types_convertible_p (type, TREE_TYPE (rhs), true))
     return convert (type, rhs);
   /* Arithmetic types all interconvert, and enum is treated like int.  */
   else if ((codel == INTEGER_TYPE || codel == REAL_TYPE
@@ -4604,7 +4604,7 @@ digest_init (tree type, tree init, bool strict_string, int require_constant)
      below and handle as a constructor.  */
   if (code == VECTOR_TYPE
       && TREE_CODE (TREE_TYPE (inside_init)) == VECTOR_TYPE
-      && vector_types_convertible_p (TREE_TYPE (inside_init), type)
+      && vector_types_convertible_p (TREE_TYPE (inside_init), type, true)
       && TREE_CONSTANT (inside_init))
     {
       if (TREE_CODE (inside_init) == VECTOR_CST
diff --git a/gcc/c.opt b/gcc/c.opt
index 5500d08..c5bf9be 100644
--- a/gcc/c.opt
+++ b/gcc/c.opt
@@ -583,6 +583,10 @@ Inject friend functions into enclosing namespace
 flabels-ok
 C++ ObjC++
 
+flax-vector-conversions
+C ObjC C++ ObjC++
+Allow implicit conversions between vectors with differing numbers of subparts and/or differing element types.
+
 fms-extensions
 C ObjC C++ ObjC++
 Don't warn about uses of Microsoft extensions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a7d64b2..579b4a3 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -15998,7 +15998,7 @@ ix86_init_mmx_sse_builtins (void)
   const struct builtin_description * d;
   size_t i;
 
-  tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode);
+  tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
   tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
   tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
   tree V2DI_type_node
@@ -16007,7 +16007,7 @@ ix86_init_mmx_sse_builtins (void)
   tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
   tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
   tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
-  tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
+  tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
   tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
 
   tree pchar_type_node = build_pointer_type (char_type_node);
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index dacb6d0..dc9cb83 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -332,7 +332,7 @@ NAME (T a1, U a2) \
 __altivec_binary_pred(vec_cmplt,
   __builtin_vec_cmpgt (a2, a1))
 __altivec_binary_pred(vec_cmple,
-  __builtin_altivec_cmpge (a2, a1))
+  __builtin_vec_cmpge (a2, a1))
 
 __altivec_scalar_pred(vec_all_in,
   __builtin_altivec_vcmpbfp_p (__CR6_EQ, a1, a2))
@@ -402,7 +402,7 @@ __altivec_scalar_pred(vec_any_nle,
 #undef __altivec_binary_pred
 #else
 #define vec_cmplt(a1, a2) __builtin_vec_cmpgt ((a2), (a1))
-#define vec_cmple(a1, a2) __builtin_altivec_vcmpgefp ((a2), (a1))
+#define vec_cmple(a1, a2) __builtin_vec_cmpge ((a2), (a1))
 
 #define vec_all_in(a1, a2) __builtin_altivec_vcmpbfp_p (__CR6_EQ, (a1), (a2))
 #define vec_any_out(a1, a2) __builtin_altivec_vcmpbfp_p (__CR6_EQ_REV, (a1), (a2))
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index d4988bd..d8f1075 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -224,17 +224,17 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
@@ -242,17 +242,17 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
@@ -260,11 +260,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
-    RS6000_BTI_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
-    RS6000_BTI_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 
   /* Binary AltiVec builtins.  */
   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
@@ -578,31 +578,23 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
-    RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
+
   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
-    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
-    RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
+
   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
-    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
-  { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
-    RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+
   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+
   { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
@@ -620,29 +612,29 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
-    RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
-    RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+    RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
-    RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
-    RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
+    RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
-    RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
+    RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
-    RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
+    RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 0e7898a..a8d9f78 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,12 @@
+2007-01-08  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* call.c (standard_conversion): Pass flag to
+	vector_types_convertible_p to disallow emission of note.
+	* typeck.c (convert_for_assignment): Pass flag to
+	vector_types_convertible_p to allow emission of note.
+	(ptr_reasonably_similar): Pass flag to vector_types_convertible_p
+	to disallow emission of note.
+
 2007-01-07  Manuel Lopez-Ibanez  <manu@gcc.gnu.org>
 
 	PR c++/28986
diff --git a/gcc/cp/call.c b/gcc/cp/call.c
index 3418703..1cbb4a8 100644
--- a/gcc/cp/call.c
+++ b/gcc/cp/call.c
@@ -842,7 +842,7 @@ standard_conversion (tree to, tree from, tree expr, bool c_cast_p,
 	conv->rank = cr_promotion;
     }
   else if (fcode == VECTOR_TYPE && tcode == VECTOR_TYPE
-	   && vector_types_convertible_p (from, to))
+	   && vector_types_convertible_p (from, to, false))
     return build_conv (ck_std, to, conv);
   else if (!(flags & LOOKUP_CONSTRUCTOR_CALLABLE)
 	   && IS_AGGR_TYPE (to) && IS_AGGR_TYPE (from)
diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c
index 2a6c8f8..7c573f6 100644
--- a/gcc/cp/typeck.c
+++ b/gcc/cp/typeck.c
@@ -6296,7 +6296,7 @@ convert_for_assignment (tree type, tree rhs,
   coder = TREE_CODE (rhstype);
 
   if (TREE_CODE (type) == VECTOR_TYPE && coder == VECTOR_TYPE
-      && vector_types_convertible_p (type, rhstype))
+      && vector_types_convertible_p (type, rhstype, true))
     return convert (type, rhs);
 
   if (rhs == error_mark_node || rhstype == error_mark_node)
@@ -6863,7 +6863,7 @@ ptr_reasonably_similar (tree to, tree from)
 	continue;
 
       if (TREE_CODE (to) == VECTOR_TYPE
-	  && vector_types_convertible_p (to, from))
+	  && vector_types_convertible_p (to, from, false))
 	return 1;
 
       if (TREE_CODE (to) == INTEGER_TYPE
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0b1ab49..d83f661 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -169,7 +169,7 @@ in the following sections.
 -fno-asm  -fno-builtin  -fno-builtin-@var{function} @gol
 -fhosted  -ffreestanding -fopenmp -fms-extensions @gol
 -trigraphs  -no-integrated-cpp  -traditional  -traditional-cpp @gol
--fallow-single-precision  -fcond-mismatch @gol
+-fallow-single-precision  -fcond-mismatch -flax-vector-conversions @gol
 -fsigned-bitfields  -fsigned-char @gol
 -funsigned-bitfields  -funsigned-char}
 
@@ -1381,6 +1381,12 @@ Allow conditional expressions with mismatched types in the second and
 third arguments.  The value of such an expression is void.  This option
 is not supported for C++.
 
+@item -flax-vector-conversions
+@opindex flax-vector-conversions
+Allow implicit conversions between vectors with differing numbers of
+elements and/or incompatible element types.  This option should not be
+used for new code.
+
 @item -funsigned-char
 @opindex funsigned-char
 Let the type @code{char} be unsigned, like @code{unsigned char}.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 47dce00..80eeb11 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,19 @@
 2007-01-08  Mark Shinwell  <shinwell@codesourcery.com>
 
+	* gcc.target/i386/20020531-1.c: Use "char" not "unsigned char"
+	in __v8qi typedef.
+	* gcc.target/powerpc/altivec-vec-merge.c (foo): Add casts.
+	* gcc.dg/simd-1.c: Update dg-error directives to reflect new
+	compiler behaviour.
+	* gcc.dg/simd-5.c: Likewise.
+	* gcc.dg/simd-6.c: Likewise.
+	* g++.dg/conversion/simd1.C: Likewise.
+	* g++.dg/conversion/simd3.C: Likewise.
+	* g++.dg/ext/attribute-test-2.C (data): Add "vs" member.
+	(main): Use it.
+
+2007-01-08  Mark Shinwell  <shinwell@codesourcery.com>
+
 	PR tree-optimization/29877
 	* gcc.dg/pr16194.c: Skip test entirely if we don't know the
 	name of a hard register for the target concerned.  Adjust dg-error
diff --git a/gcc/testsuite/g++.dg/conversion/simd1.C b/gcc/testsuite/g++.dg/conversion/simd1.C
index d9406fa..0a5302d 100644
--- a/gcc/testsuite/g++.dg/conversion/simd1.C
+++ b/gcc/testsuite/g++.dg/conversion/simd1.C
@@ -5,9 +5,9 @@
 
 #define vector __attribute__((vector_size(16)))
 
-vector signed int vld (int a1, const vector signed int *a2) { return *a2; } /* { dg-error "near match" } */
+vector signed int vld (int a1, const vector signed int *a2) { return *a2; } /* { dg-error "vld" } */
 /* { dg-warning "vector returned by ref" "" { target { powerpc*-*-linux* && ilp32 } }  8 } */
-vector signed short vld (int a1, const vector signed short *a2) { return *a2; } /* { dg-error "near match" } */
+vector signed short vld (int a1, const vector signed short *a2) { return *a2; } /* { dg-error "vld" } */
 
 extern int i;
 extern vector signed short vss;
@@ -17,7 +17,7 @@ extern const vector signed short *cvssp;
 
 void foo ()
 {
-  vss = vld(i, vscp);        /* { dg-error "no match" } */
+  vss = vld(i, vscp);        /* { dg-error "no matching function for call" } */
   vss = vld(i, vssp);
   vss = vld(i, cvssp);
 }
diff --git a/gcc/testsuite/g++.dg/conversion/simd3.C b/gcc/testsuite/g++.dg/conversion/simd3.C
index f7b28d4..cdc2ed6 100644
--- a/gcc/testsuite/g++.dg/conversion/simd3.C
+++ b/gcc/testsuite/g++.dg/conversion/simd3.C
@@ -10,6 +10,6 @@ unsigned int __attribute__((vector_size(16))) e;
 void foo()
 {
 	b + d; /* { dg-error "invalid operands to binary" } */
-	d += e;
+	d += e; /* { dg-error "use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts.*cannot convert 'unsigned int __vector__' to 'int __vector__' in assignment" } */
 	d2 += d;
 }
diff --git a/gcc/testsuite/g++.dg/ext/attribute-test-2.C b/gcc/testsuite/g++.dg/ext/attribute-test-2.C
index 9a19706..8347cc1 100644
--- a/gcc/testsuite/g++.dg/ext/attribute-test-2.C
+++ b/gcc/testsuite/g++.dg/ext/attribute-test-2.C
@@ -15,8 +15,8 @@ public:
      return (__attribute__((vector_size(16))) short) vec;
    }
 
-   operator __attribute__((vector_size(16))) int (void) {
-     return (__attribute__((vector_size(16))) int) vec1;
+   operator __attribute__((vector_size(16))) unsigned int (void) {
+     return (__attribute__((vector_size(16))) unsigned int) vec1;
    }
 
    vector_holder () {
@@ -30,6 +30,7 @@ public:
 union u {
               char f[16];
               vector unsigned int v;
+              vector short vs;
 } data;
 
 
@@ -37,10 +38,10 @@ vector_holder vh;
 
 int main()
 {
-  data.v = (__attribute__((vector_size(16))) short) vh;
+  data.vs = (__attribute__((vector_size(16))) short) vh;
   if (data.f[0] != 'a' || data.f[15] != 'd')
     abort(); 
-  data.v = (__attribute__((vector_size(16))) int) vh;
+  data.v = (__attribute__((vector_size(16))) unsigned int) vh;
   if (data.f[0] != 'm' || data.f[15] != 'p')
     abort(); 
 
diff --git a/gcc/testsuite/gcc.dg/simd-1.c b/gcc/testsuite/gcc.dg/simd-1.c
index faf33dd..08be780 100644
--- a/gcc/testsuite/gcc.dg/simd-1.c
+++ b/gcc/testsuite/gcc.dg/simd-1.c
@@ -32,7 +32,7 @@ hanneke ()
   e = (typeof (e)) a;
 
   /* Different signed SIMD assignment.  */
-  f = a;
+  f = a; /* { dg-error "use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts.*35: error: incompatible types in assignment" } */
 
   /* Casted different signed SIMD assignment.  */
   f = (uv4si) a;
diff --git a/gcc/testsuite/gcc.dg/simd-5.c b/gcc/testsuite/gcc.dg/simd-5.c
index 31a13d9..37df370 100644
--- a/gcc/testsuite/gcc.dg/simd-5.c
+++ b/gcc/testsuite/gcc.dg/simd-5.c
@@ -4,4 +4,4 @@
 /* Ensure that we don't need a typedef to initialize a vector type.  */
 #define vector __attribute__ ((vector_size (8)))
 vector char x = (vector char) {1,2,3,4,5,6,7,8}; /* { dg-bogus "initializer" } */
-vector char y = (vector short) {1,2,3,4}; /* { dg-error "initializer" } */
+vector char y = (vector short) {1,2,3,4}; /* { dg-error "use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts.*incompatible types in initialization" } */
diff --git a/gcc/testsuite/gcc.dg/simd-6.c b/gcc/testsuite/gcc.dg/simd-6.c
index b1d244a..a88f13f 100644
--- a/gcc/testsuite/gcc.dg/simd-6.c
+++ b/gcc/testsuite/gcc.dg/simd-6.c
@@ -4,4 +4,4 @@
 /* Ensure that we don't need a typedef to initialize a vector type.  */
 #define vector __attribute__ ((vector_size (8)))
 vector char x = (vector char) {1,2,3,4,5,6,7,8}; /* { dg-bogus "initializer" } */
-vector char y = (vector short) {1,2,3,4}; /* { dg-error "initializer" } */
+vector char y = (vector short) {1,2,3,4}; /* { dg-error "use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts.*incompatible types in initialization" } */
diff --git a/gcc/testsuite/gcc.target/i386/20020531-1.c b/gcc/testsuite/gcc.target/i386/20020531-1.c
index dfefc17..9ee67b9 100644
--- a/gcc/testsuite/gcc.target/i386/20020531-1.c
+++ b/gcc/testsuite/gcc.target/i386/20020531-1.c
@@ -4,7 +4,7 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
 /* { dg-options "-O2 -mmmx" } */
 
-typedef unsigned char __v8qi __attribute__ ((vector_size (8)));
+typedef char __v8qi __attribute__ ((vector_size (8)));
 extern void abort (void);
 extern void exit (int);
 
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
index 0e92a07..e6027bd 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
@@ -96,7 +96,7 @@ void foo(char *bS, char *bS_edge, int field_MBAFF, int top){
     v6   = (vector signed short) vec_cmpeq ((vector signed char) v2, (vector signed char) v3);
   }
   else  {
-    v4 = v5 = v6 = vec_nor (v_zero, v_zero);
+    v4 = v5 = v6 = (vector signed short) vec_nor (v_zero, v_zero);
   }
 
   tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);
@@ -335,7 +335,7 @@ void foo(char *bS, char *bS_edge, int field_MBAFF, int top){
     v10  = (vector signed short) vec_cmpeq ((vector signed char) v10, (vector signed char) v11);
   }
   else  {
-    v8 = v9 = v10 = vec_nor (v_zero, v_zero);
+    v8 = v9 = v10 = (vector signed short) vec_nor (v_zero, v_zero);
   }
 
   tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);