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author | Andrew Burgess <andrew.burgess@embecosm.com> | 2015-12-19 19:22:51 +0000 |
---|---|---|
committer | Joern Rennecke <amylaar@gcc.gnu.org> | 2015-12-19 19:22:51 +0000 |
commit | 0086bd992fed3bf491be0c3f5387c4f6c9f2cace (patch) | |
tree | 39697eb359f7ef88307259faee16f4d5aa7a029d | |
parent | a278e2017797a7ba7f807ca93ce0c06a37c8bdaf (diff) | |
download | gcc-0086bd992fed3bf491be0c3f5387c4f6c9f2cace.zip gcc-0086bd992fed3bf491be0c3f5387c4f6c9f2cace.tar.gz gcc-0086bd992fed3bf491be0c3f5387c4f6c9f2cace.tar.bz2 |
arc.md (*loadqi_update): Use new 'any_mem_operand' and fix RTL pattern to include the plus.
gcc:
2015-12-19 Andrew Burgess <andrew.burgess@embecosm.com>
* config/arc/arc.md (*loadqi_update): Use new 'any_mem_operand'
and fix RTL pattern to include the plus.
(*load_zeroextendqisi_update): Likewise.
(*load_signextendqisi_update): Likewise.
(*loadhi_update): Likewise.
(*load_zeroextendhisi_update): Likewise.
(*load_signextendhisi_update): Likewise.
(*loadsi_update): Likewise.
(*loadsf_update): Likewise.
* config/arc/predicates.md (load_update_operand): Delete.
(any_mem_operand): New predicate.
gcc/testsuite:
2015-12-19 Andrew Burgess <andrew.burgess@embecosm.com>
* gcc.target/arc/load-update.c: New file.
From-SVN: r231849
-rw-r--r-- | gcc/ChangeLog | 14 | ||||
-rw-r--r-- | gcc/config/arc/arc.md | 48 | ||||
-rw-r--r-- | gcc/config/arc/predicates.md | 21 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arc/load-update.c | 20 |
5 files changed, 65 insertions, 42 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d024128..b0ec3c7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2015-12-19 Andrew Burgess <andrew.burgess@embecosm.com> + + * config/arc/arc.md (*loadqi_update): Use new 'any_mem_operand' + and fix RTL pattern to include the plus. + (*load_zeroextendqisi_update): Likewise. + (*load_signextendqisi_update): Likewise. + (*loadhi_update): Likewise. + (*load_zeroextendhisi_update): Likewise. + (*load_signextendhisi_update): Likewise. + (*loadsi_update): Likewise. + (*loadsf_update): Likewise. + * config/arc/predicates.md (load_update_operand): Delete. + (any_mem_operand): New predicate. + 2015-12-19 Sujoy Saraswati <sujoy.saraswati@hpe.com> PR tree-optimization/61441 diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index ac181a9..7ca4431 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1114,9 +1114,9 @@ ;; Note: loadqi_update has no 16-bit variant (define_insn "*loadqi_update" [(set (match_operand:QI 3 "dest_reg_operand" "=r,r") - (match_operator:QI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")])) + (match_operator:QI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])) (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1126,9 +1126,9 @@ (define_insn "*load_zeroextendqisi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (zero_extend:SI (match_operator:QI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")]))) + (zero_extend:SI (match_operator:QI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))) (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1138,9 +1138,9 @@ (define_insn "*load_signextendqisi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (sign_extend:SI (match_operator:QI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")]))) + (sign_extend:SI (match_operator:QI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))) (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1164,9 +1164,9 @@ ;; Note: no 16-bit variant for this pattern (define_insn "*loadhi_update" [(set (match_operand:HI 3 "dest_reg_operand" "=r,r") - (match_operator:HI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")])) + (match_operator:HI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])) (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1176,9 +1176,9 @@ (define_insn "*load_zeroextendhisi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (zero_extend:SI (match_operator:HI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")]))) + (zero_extend:SI (match_operator:HI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))) (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1189,9 +1189,9 @@ ;; Note: no 16-bit variant for this instruction (define_insn "*load_signextendhisi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (sign_extend:SI (match_operator:HI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")]))) + (sign_extend:SI (match_operator:HI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))) (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1214,9 +1214,9 @@ ;; No 16-bit variant for this instruction pattern (define_insn "*loadsi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (match_operator:SI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")])) + (match_operator:SI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])) (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1238,9 +1238,9 @@ (define_insn "*loadsf_update" [(set (match_operand:SF 3 "dest_reg_operand" "=r,r") - (match_operator:SF 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")])) + (match_operator:SF 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])) (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md index de0735a..268ff7e 100644 --- a/gcc/config/arc/predicates.md +++ b/gcc/config/arc/predicates.md @@ -460,24 +460,6 @@ } ) -;; Return true if OP is valid load with update operand. -(define_predicate "load_update_operand" - (match_code "mem") -{ - if (GET_CODE (op) != MEM - || GET_MODE (op) != mode) - return 0; - op = XEXP (op, 0); - if (GET_CODE (op) != PLUS - || GET_MODE (op) != Pmode - || !register_operand (XEXP (op, 0), Pmode) - || !nonmemory_operand (XEXP (op, 1), Pmode)) - return 0; - return 1; - -} -) - ;; Return true if OP is valid store with update operand. (define_predicate "store_update_operand" (match_code "mem") @@ -817,3 +799,6 @@ (define_predicate "mem_noofs_operand" (and (match_code "mem") (match_code "reg" "0"))) + +(define_predicate "any_mem_operand" + (match_code "mem"))
\ No newline at end of file diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 20ac322..d1ebe8d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-12-19 Andrew Burgess <andrew.burgess@embecosm.com> + + * gcc.target/arc/load-update.c: New file. + 2015-12-18 Patrick Palka <ppalka@gcc.gnu.org> PR c++/68978 diff --git a/gcc/testsuite/gcc.target/arc/load-update.c b/gcc/testsuite/gcc.target/arc/load-update.c new file mode 100644 index 0000000..8299cb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/load-update.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +/* This caused a segfault due to incorrect rtl pattern in some + instructions. */ + +int a, d; +char *b; + +void fn1() +{ + char *e = 0; + for (; d; ++a) + { + char c = b [0]; + *e++ = '.'; + *e++ = 4; + *e++ = "0123456789abcdef" [c & 5]; + } +} |