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path: root/sim/testsuite/frv/addcc.cgs
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# frv testcase for addcc $GRi,$GRj,$GRk,$ICCi_1
# mach: all

	.include "testutils.inc"

	start

	.global addcc
addcc:
	set_gr_immed   	1,gr7
	set_gr_immed   	2,gr8
	set_icc         0x0f,0		; Set mask opposite of expected
	addcc      	gr7,gr8,gr8,icc0
	test_icc	0 0 0 0 icc0
	test_gr_immed  	3,gr8

	set_gr_limmed  	0x7fff,0xffff,gr7
	set_gr_immed   	1,gr8
	set_icc         0x05,0		; Set mask opposite of expected
	addcc		gr7,gr8,gr8,icc0
	test_icc	1 0 1 0 icc0
	test_gr_limmed 	0x8000,0x0000,gr8

	set_icc         0x08,0		; Set mask opposite of expected
	addcc		gr8,gr8,gr8,icc0
	test_icc	0 1 1 1 icc0
	test_gr_immed  	0,gr8

	set_gr_limmed	0x8000,0x0000,gr8
	set_icc         0x08,0		; Set mask opposite of expected
	addcc		gr8,gr8,gr8,icc0; test zero, carry and overflow bits
	test_icc	0 1 1 1 icc0
	test_gr_immed  	0,gr8


	pass