aboutsummaryrefslogtreecommitdiff
path: root/sim/testsuite/d10v/t-rdt.s
blob: 947da8644d5600032eba6dbd0259c0059731bd79 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
# mach: all
# output:
# sim: --environment operating
# as: -W

.include "t-macros.i"

	start

	PSW_BITS = PSW_C|PSW_F0|PSW_F1

	ldi	r6, #success@word
	mvtc	r6, dpc
	ldi	r6, #PSW_BITS
	mvtc	r6, dpsw

test_rdt:
	RTD
	exit47

success:
	checkpsw2 1 PSW_BITS
	exit0