| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-02-13 | sim: riscv: Add support for compressed integer instructions | Jaydeep Patil | 1 | -1/+1 | |
| Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com> | |||||
| 2021-02-04 | sim: riscv: new port | Mike Frysinger | 1 | -0/+7 | |
| This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better. | |||||
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index : riscv-gnu-toolchain/binutils.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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