| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 1996-12-02 | * simops.c: Fix "mov am, dn". | Jeff Law | 1 | -1/+1 | |
| Fixes more c-torture problems. | |||||
| 1996-12-01 | * simops.c: Fix more bugs in "add imm,an" and | Jeff Law | 1 | -8/+8 | |
| "add imm,dn". Fixes a half-dozen (of several hundred :( c-torture failures. | |||||
| 1996-11-27 | * simops.c: Fix bugs in "movm" and "add imm,an". | Jeff Law | 1 | -17/+17 | |
| main(){write (0, "hello world\n", 13);} works! | |||||
| 1996-11-27 | * simops.c: Don't lose the upper 24 bits of the return | Jeff Law | 1 | -16/+150 | |
| pointer in "call" and "calls" instructions. Rough cut at emulated system calls. | |||||
| 1996-11-27 | * simops.c: Implement the remaining 5, 6 and 7 byte instructions. | Jeff Law | 1 | -50/+166 | |
| Everything except the extended instructions, the loop instructions, trap, rti, and rtm. | |||||
| 1996-11-27 | * simops.c Implement remaining 4 byte instructions. | Jeff Law | 1 | -38/+142 | |
| 1996-11-27 | * simops.c Implement remaining 3 byte instructions. | Jeff Law | 1 | -32/+118 | |
| Moving right along... | |||||
| 1996-11-27 | * simops.c: Implement remaining 2 byte instructions. Call | Jeff Law | 1 | -23/+115 | |
| abort for instructions we're not implementing now. | |||||
| 1996-11-27 | * simops.c: Implement lots of random instructions. | Jeff Law | 1 | -129/+640 | |
| Implments most instructions with first nibble 0x0 - 0xe and those with the first byte 0xf0 - 0xf2. | |||||
| 1996-11-27 | * simops.c: Implement "movm" and "bCC" insns. | Jeff Law | 1 | -7/+158 | |
| Function calls and conditional branches work! | |||||
| 1996-11-27 | * mn10300_sim.h (_state): Add another register (MDR). | Jeff Law | 1 | -8/+192 | |
| (REG_MDR): Define. * simops.c: Implement "cmp", "calls", "rets", "jmp" and a few additional random insns. We can now function calls. We get out of crt0 into main now, then lose when calls are nested (because don't handle movm yet). | |||||
| 1996-11-26 | * mn10300_sim.h (PSW_*): Define for CC status tracking. | Jeff Law | 1 | -19/+295 | |
| (REG_D0, REG_A0, REG_SP): Define. * simops.c: Implement "add", "addc" and a few other random instructions. Starting to simulate instructions for the mn10300. Executes some of the crt0 code now! | |||||
| 1996-11-25 | * Makefile.in, config.in, configure, configure.in: New files. | Jeff Law | 1 | -0/+1228 | |
| * gencode.c, interp.c, mn10300_sim.h, simops.c: New files. Skeleton mn10300 simulator | |||||
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index : riscv-gnu-toolchain/binutils.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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