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| author | Jeff Law <law@redhat.com> | 1996-12-01 23:10:04 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1996-12-01 23:10:04 +0000 |
| commit | 6db7fc49d29a545d85cdfd563786fe0899a50016 (patch) | |
| tree | 2eae842fc1067945243417da1af7706a2869987f /sim/mn10300/simops.c | |
| parent | c5c449520283809b6e77655a70cb9082f76a9e7c (diff) | |
| download | binutils-6db7fc49d29a545d85cdfd563786fe0899a50016.zip binutils-6db7fc49d29a545d85cdfd563786fe0899a50016.tar.gz binutils-6db7fc49d29a545d85cdfd563786fe0899a50016.tar.bz2 | |
* simops.c: Fix more bugs in "add imm,an" and
"add imm,dn".
Fixes a half-dozen (of several hundred :( c-torture failures.
Diffstat (limited to 'sim/mn10300/simops.c')
| -rw-r--r-- | sim/mn10300/simops.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c index 20cd976..e2f1ffd 100644 --- a/sim/mn10300/simops.c +++ b/sim/mn10300/simops.c @@ -1034,10 +1034,10 @@ void OP_FAC00000 () int z, c, n, v; unsigned long reg1, imm, value; - reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)]; + reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)]; imm = SEXT16 (insn & 0xffff); value = reg1 + imm; - State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value; + State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value; z = (value == 0); n = (value & 0x80000000); @@ -1056,10 +1056,10 @@ void OP_FCC00000 () int z, c, n, v; unsigned long reg1, imm, value; - reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)]; + reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)]; imm = ((insn & 0xffff) << 16) | extension; value = reg1 + imm; - State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value; + State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value; z = (value == 0); n = (value & 0x80000000); @@ -1100,10 +1100,10 @@ void OP_FAD00000 () int z, c, n, v; unsigned long reg1, imm, value; - reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)]; + reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)]; imm = SEXT16 (insn & 0xffff); value = reg1 + imm; - State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value; + State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value; z = (value == 0); n = (value & 0x80000000); @@ -1122,10 +1122,10 @@ void OP_FCD00000 () int z, c, n, v; unsigned long reg1, imm, value; - reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)]; + reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)]; imm = ((insn & 0xffff) << 16) | extension; value = reg1 + imm; - State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value; + State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value; z = (value == 0); n = (value & 0x80000000); |