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2024-06-05arm: remove disassembly support for the FPA co-processorRichard Earnshaw1-196/+1
Remove the FPA support from the disassembler. This entails a couple of testsuite fixes where we were (probably incorrectly) disassembling a generic co-processor instruction using the legacy FPA opcodes.
2024-06-05Fix illegal memory access when bfd_get_section_contents is called with a ↵Nick Clifton1-0/+7
NULL section pointer. PR 31843
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett1-0/+26
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvmem` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVmem as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mem-fail-march.d: New test. * testsuite/gas/riscv/cv-mem-fail-march.l: New test. * testsuite/gas/riscv/cv-mem-fail-march.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-mem-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-mem-lbpost.d: New test. * testsuite/gas/riscv/cv-mem-lbpost.s: New test. * testsuite/gas/riscv/cv-mem-lbrr.d: New test. * testsuite/gas/riscv/cv-mem-lbrr.s: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lbupost.d: New test. * testsuite/gas/riscv/cv-mem-lbupost.s: New test. * testsuite/gas/riscv/cv-mem-lburr.d: New test. * testsuite/gas/riscv/cv-mem-lburr.s: New test. * testsuite/gas/riscv/cv-mem-lburrpost.d: New test. * testsuite/gas/riscv/cv-mem-lburrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhpost.d: New test. * testsuite/gas/riscv/cv-mem-lhpost.s: New test. * testsuite/gas/riscv/cv-mem-lhrr.d: New test. * testsuite/gas/riscv/cv-mem-lhrr.s: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhrrpost.s: New test. * testsuite/gas/riscv/cv-mem-lhupost.d: New test. * testsuite/gas/riscv/cv-mem-lhupost.s: New test. * testsuite/gas/riscv/cv-mem-lhurr.d: New test. * testsuite/gas/riscv/cv-mem-lhurr.s: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.d: New test. * testsuite/gas/riscv/cv-mem-lhurrpost.s: New test. * testsuite/gas/riscv/cv-mem-lwpost.d: New test. * testsuite/gas/riscv/cv-mem-lwpost.s: New test. * testsuite/gas/riscv/cv-mem-lwrr.d: New test. * testsuite/gas/riscv/cv-mem-lwrr.s: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.d: New test. * testsuite/gas/riscv/cv-mem-lwrrpost.s: New test. * testsuite/gas/riscv/cv-mem-sbpost.d: New test. * testsuite/gas/riscv/cv-mem-sbpost.s: New test. * testsuite/gas/riscv/cv-mem-sbrr.d: New test. * testsuite/gas/riscv/cv-mem-sbrr.s: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.d: New test. * testsuite/gas/riscv/cv-mem-sbrrpost.s: New test. * testsuite/gas/riscv/cv-mem-shpost.d: New test. * testsuite/gas/riscv/cv-mem-shpost.s: New test. * testsuite/gas/riscv/cv-mem-shrr.d: New test. * testsuite/gas/riscv/cv-mem-shrr.s: New test. * testsuite/gas/riscv/cv-mem-shrrpost.d: New test. * testsuite/gas/riscv/cv-mem-shrrpost.s: New test. * testsuite/gas/riscv/cv-mem-swpost.d: New test. * testsuite/gas/riscv/cv-mem-swpost.s: New test. * testsuite/gas/riscv/cv-mem-swrr.d: New test. * testsuite/gas/riscv/cv-mem-swrr.s: New test. * testsuite/gas/riscv/cv-mem-swrrpost.d: New test. * testsuite/gas/riscv/cv-mem-swrrpost.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvmem string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVmem. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVmem. (enum riscv_insn_class): Add the XCVmem instruction class. opcodes/ChangeLog: * riscv-opc.c: Add XCVmem instructions.
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett2-0/+8
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> Nazareno Bruschi <nazareno.bruschi@embecosm.com> Lin Sinan include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbi as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-bi-beqimm.d: New test. * testsuite/gas/riscv/cv-bi-beqimm.s: New test. * testsuite/gas/riscv/cv-bi-bneimm.d: New test. * testsuite/gas/riscv/cv-bi-bneimm.s: New test. * testsuite/gas/riscv/cv-bi-fail-march.d: New test. * testsuite/gas/riscv/cv-bi-fail-march.l: New test. * testsuite/gas/riscv/cv-bi-fail-march.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvbi string. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbi. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbi. (enum riscv_insn_class): Add the XCVbi instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add disassembly for new operand. * riscv-opc.c: Add XCVbi instructions.
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+3
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Note XCVelw as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-elw-fail.d: New test. * testsuite/gas/riscv/cv-elw-fail.l: New test. * testsuite/gas/riscv/cv-elw-fail.s: New test. * testsuite/gas/riscv/cv-elw-fail-march.d: New test. * testsuite/gas/riscv/cv-elw-fail-march.l: New test. * testsuite/gas/riscv/cv-elw-fail-march.s: New test. * testsuite/gas/riscv/cv-elw-pass.d: New test. * testsuite/gas/riscv/cv-elw-pass.s: New test. * testsuite/gas/riscv/march-help.l: Add xcvelw string. opcodes/ChangeLog: * riscv-opc.c: (riscv_opcode) Add event load instructions. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction opcode macros. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich4-5657/+5662
Except for very few insns mnemonic suffixes aren't permitted in Intel syntax. Warn about such for now, indicating that they will be outright refused down the road. While fiddling with testcases to address fallout, drop a few things which should never have been tested as valid Intel syntax. Also add a previously missing line to simd-suffix.d.
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com6-130/+252
Introduces instructions for the SVE2 lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions use new SVE2 vector operands. They are called SVE_Zm1_23_INDEX, SVE_Zm2_22_INDEX, and Zm3_12_INDEX and they have 1 bit, 2 bit, and 3 bit indices respectively. The lsb and width of these new operands are the same as many existing operands but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h. We made a design choice for the second operand of the halfword variant of luti4 with two register tables. We could have either defined a new operand, like SVE_Znx2, or we could have use the existing operand SVE_ZnxN. With the new operand, we would need to implement constraints on register lists based on either operand or opcode flag. With existing operand, we could just existing constraint checks using opcode flag. We chose the second approach and went with SVE_ZnxN and added opcode flag to enforce lengths of vector register list operands. This way, we can reuse the existing constraint check logic.
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com10-362/+509
Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links: * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en These instructions needed definition of some new operands. We will first discuss operands for the third operand of the instructions and then discuss a vector register list operand needed for the second operand. The third operands are vectors with bit indices and without type qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12 and they have 1 bit, 2 bit, and 3 bit indices respectively. For these new operands, we defined new parsing case branch. The lsb and width of these operands are the same as many existing but the convention is to give different names to fields that serve different purpose so we introduced new fields in aarch64-opc.c and aarch64-opc.h for these new operands. For the second operand of these instructions, we introduced a new operand called LVn_LUT. This represents a vector register list with stride 1. We defined new inserter and extractor for this new operand and it is encoded in FLD_Rn. We are enforcing the number of registers in the reglist using opcode flag rather than operand flag as this is what other SIMD vector register list operands are doing. The disassembly also uses opcode flag to print the correct number of registers.
2024-05-28opcodes: add a .gitattributes file for aarch64 autogenerated file exceptionsRichard Earnshaw1-0/+3
The autogenerated files in opcodes use spaces for indentation. Changing that would be a lot of work to little benefit, so add a local override to the white-space rules, so patches apply cleanly.
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich2-16/+16
Properly reject inappropriate suffixes (No_lSuf / No_qSuf mistakenly omitted by cf665fee1d6c ["x86: re-work AVX512 embedded rounding / SAE"]), to avoid emitting bad or arbitrarily guessed instructions. Interestingly check_{long,qword}_suffix() don't help here, which perhaps is another indication that the way they work right now isn't quite appropriate. Sadly correcting just the templates breaks operand ambiguity detection, since so far that worked from a single template permitting more than one suffix. Here we have ambiguity though which can now be noticed only when taking all (matching) templates together. Therefore we need to determine further matching templates (see code comments for constraints), to then accumulate permitted suffixes across all of them.
2024-05-22aarch64: fix incorrect encoding for system register pmsdsfr_el1Matthieu Longo1-1/+1
This patch fixes a mistake in the encoding of the system register pmsdsfr_el1. Reference: https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/PMSDSFR-EL1--Sampling-Data-Source-Filter-Register?lang=en
2024-05-22Support APX zero-upperCui, Lili8-6243/+6985
This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-05-21aarch64: Fix the hyphenated disassembly comment.Srinath Parvathaneni1-2/+2
This patch fixes the following comment. - /* The hyphenated form is preferred for disassembly if there are - more than two registers in the list, and the register numbers are monotonically increasing in increments of one. */ + /* The hyphenated form is preferred for disassembly if there is + more than one register in the list, and the register numbers are monotonically increasing in increments of one. */
2024-05-20aarch64: Add support for the fpmr system registerClaudio Bantaloukas1-0/+1
2024-05-17aarch64: correct SVE2.1 ld2q (scalar plus scalar)Jan Beulich2-12/+21
It's opcode was wrong, as was e.g. easily visible from the inappropriate testcase expectation.
2024-05-17aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate)Jan Beulich1-4/+4
Like their byte, half, word, and doubleword counterparts their immediates are multiples of 3 / 4 respectively.
2024-05-16aarch64: fp8 convert and scale - add sme2 insn variantsVictor Do Nascimento2-136/+328
Add the SME2 variant of the FP8 convert and scale instructions, enabled at assembly-time using the `+sme2+fp8' architectural extension flag. More specifically, support is added for the following instructions: Multi-vector floating-point convert from FP8 to BFloat16 (in-order): ----------------------------------------------- - bf1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B - bf2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B Multi-vector floating-point convert from FP8 to deinterleaved BFloat16: ----------------------------------------------- - bf1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B - bf2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B Multi-vector floating-point convert from BFloat16 to packed FP8 format: ------------------------------------------------- - bfcvt <Zd>.B, { <Zn1>.H-<Zn2>.H } Multi-vector floating-point convert from FP8 to half-precision (in-order): ----------------------------------------------- - f1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B - f2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B Multi-vector floating-point convert from FP8 to deinterleaved half-precision: ----------------------------------------------- - f1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B - f2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B Multi-vector floating-point convert from half-precision to packed FP8 format: ------------------------------------------------------- fcvt_2h Multi-vector floating-point convert from single-precision to packed FP8 format: --------------------------------------------------------- fcvt_4s Multi-vector floating-point convert from single-precision to interleaved FP8 format: --------------------------------------------------------- - fcvtn <Zd>.B, { <Zn1>.S-<Zn4>.S } Multi-vector floating-point adjust exponent by vector: ------------------------------------------------------ - fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H - fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S }, <Zm>.S - fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D }, <Zm>.D Multi-vector floating-point adjust exponent: -------------------------------------------- - fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H - <Zm2>.H } - fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S }, { <Zm1>.S - <Zm2>.S } - fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D }, { <Zm1>.D - <Zm2>.D }
2024-05-16aarch64: fp8 convert and scale - add sve2 insn variantsVictor Do Nascimento2-31/+183
Add the SVE2 variant of the FP8 convert and scale instructions, enabled at assembly-time using the `+sve2+fp8' architectural extension flag. More specifically, support is added for the following instructions: FP8 convert to BFloat16 (bottom/top): ------------------------------------- - bf1cvt Z<d>.H, Z<n>.B - bf2cvt Z<d>.H, Z<n>.B - bf1cvtlt Z<d>.H, Z<n>.B - bf2cvtlt Z<d>.H, Z<n>.B FP8 convert to half-precision (bottom/top): ------------------------------------------- - f1cvt Z<d>.H, Z<n>.B - f2cvt Z<d>.H, Z<n>.B - f1cvtlt Z<d>.H, Z<n>.B - f2cvtlt Z<d>.H, Z<n>.B BFloat16/half-precision convert, narrow and interleave to FP8: ------------------------------------------- - bfcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H } - fcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H } Single-precision convert, narrow and interleave to FP8 (bottom/top): ----------------------------------------------- - fcvtnb Z<d>.B, { Z<n>1.S - Z<n>2.S } - fcvtnt Z<d>.B, { Z<n>1.S - Z<n>2.S }
2024-05-16aarch64: fp8 convert and scale - Add advsimd insn variantsVictor Do Nascimento2-36/+220
Add the advanced SIMD variant of the FP8 convert and scale instructions, enabled at assembly-time using the `+fp8' architectural extension flag. More specifically, support is added for the following instructions: FP8 convert to BFloat16 (vector): --------------------------------- - bf1cvtl V<d>.8H, V<n>.8B - bf2cvtl V<d>.8H, V<n>.8B - bf1cvtl2 V<d>.8H, V<n>.16B - bf2cvtl2 V<d>.8H, V<n>.16B FP8 convert to half-precision (vector): --------------------------------------- - f1cvtl V<d>.8H, V<n>.8B - f2cvtl V<d>.8H, V<n>.8B - f1cvtl2 V<d>.8H, V<n>.16B - f2cvtl2 V<d>.8H, V<n>.16B Single-precision to FP8 convert and narrow (vector): ---------------------------------------------------- - fcvtn V<d>.8B, V<n>.4S, V<m>.4S - fcvtn2 V<d>.16B, V<n>.4S, V<m>.4S Half-precision to FP8 convert and narrow (vector): -------------------------------------------------- - fcvtn V<d>.8B, V<n>.4H, V<m>.4H - fcvtn V<d>.16B, V<n>.8H, V<m>.8H Floating-point adjust exponent by vector: ----------------------------------------- - fscale V<d>.4H, V<n>.4H, V<m>.4H - fscale V<d>.8H, V<n>.8H, V<m>.8H - fscale V<d>.2S, V<n>.2S, V<m>.2S - fscale V<d>.4S, V<n>.4S, V<m>.4S - fscale V<d>.2d, V<n>.2d, V<m>.2d
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento1-0/+18
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo1-0/+4
2024-05-15RISC-V: Search for mapping symbols from the last one foundJoseph Faulls1-8/+4
With previous behaviour, multiple mapping symbols within the same function would result in all the mapping symbols being searched. This could slow down disassembly dramatically. Multiple mapping symbols within a function can be a result of encoding instructions as data, like sometimes seen in random instruction generators. opcodes/ChangeLog: * riscv-dis.c (riscv_search_mapping_symbol): Use last mapping symbol if it exists.
2024-05-14arm: opcodes: remove Maverick disassembly.Richard Earnshaw1-178/+1
Remove the patterns to match Maverick co-processor instructions from the disassembly tables. This required fixing a couple of tests in the assembler testsuite where we, probably incorrectly, disassembled generic co-processor instructions as a Maverick instruction (it particularly made no sense to do this for Armv6t2 in Thumb state).
2024-05-08RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu1-88/+88
* https://github.com/riscv/riscv-b/tags Added standard B extension back, which implies Zba, Zbb and Zbs extensions. * https://github.com/riscv/riscv-zaamo-zalrsc/tags Splited standard A extension into two new extensions, Zaamo and Zalrsc. The A extension implies Zaamo and Zalrsc extensions. Not sure if we need to do the similar check as i and zicsr/zifencei. Passed riscv[32|64]-[elf/linux] binutils testcases. bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules for A and B extensions. The A implies Zaamo and Zalrsc, the B implies Zba, Zbb and Zbs. (riscv_supported_std_ext): Supported B extension with v1.0. (riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0. (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Updated. include/ * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC. opcodes/ * riscv-opc.c (riscv_opcodes): Splited standard A extension into two new extensions, Zaamo and Zalrsc. gas/ * testsuite/gas/riscv/march-imply-a.d: New testcase. * testsuite/gas/riscv/march-imply-b.d: New testcase. * testsuite/gas/riscv/attribute-01.d: Updated. * testsuite/gas/riscv/attribute-02.d: Updated. * testsuite/gas/riscv/attribute-03.d: Updated. * testsuite/gas/riscv/attribute-04.d: Updated. * testsuite/gas/riscv/attribute-05.d: Updated. * testsuite/gas/riscv/attribute-10.d: Updated. * testsuite/gas/riscv/mapping-symbols.d: Updated. * testsuite/gas/riscv/march-imply-g.d: Updated. * testsuite/gas/riscv/march-imply-unsupported.d: Updated. * testsuite/gas/riscv/march-ok-reorder.d: Updated. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated. * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated.
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili2-115/+117
gas/ChangeLog: * config/tc-i386.c (build_modrm_byte): Dropped the use of extension_opcode to encode the vvvv register. * testsuite/gas/i386/x86-64-sse2avx.d: Added new testcases. * testsuite/gas/i386/x86-64-sse2avx.s: Diito. opcodes/ChangeLog: * i386-opc.tbl: Added DstVVVV to some extension_opcode instructions. * i386-tbl.h: Regenerated.
2024-05-06x86: Drop SwapSourcesCui, Lili3-319/+319
gas/ChangeLog: * config/tc-i386.c (build_modrm_byte): Dropped the use of SWAP_SOURCES to encode the vvvv register. opcodes/ChangeLog: * i386-opc.h (SWAP_SOURCES): Dropped. (NO_DEFAULT_MASK): Adjusted the value. (ADDR_PREFIX_OP_REG): Ditto. (DISTINCT_DEST): Ditto. (IMPLICIT_STACK_OP): Ditto. (VexVVVV_SRC2): New. * i386-opc.tbl: Dropped SwapSources and replaced its VexVVVV with Src1VVVV. * i386-tbl.h: Regenerated.
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili3-655/+657
Use vexvvvv as the switch state, and replace VexVVVV with Src1VVVV. Src1VVVV means using VEX.vvvv encodes the first source register operand. The old logic did not check vexvvvv first, which made the logic here very complicated. gas/ChangeLog: * config/tc-i386.c (optimize_encoding): Replaced 1 with Src1VVVV. (build_modrm_byte): Used vexvvvv to encode the vvvv register. (s_insn): Replaced 1 with Src1VVVV. opcodes/ChangeLog: * i386-opc.h (VexVVVV_DST): Adjusted the value. (Src1VVVV): New. * i386-opc.tbl: Replaced part VexVVVV with Src1VVVV. * i386-tbl.h: Regenerated.
2024-05-03x86: tidy <sse*> templatesJan Beulich1-20/+20
Some of them no longer need a separate vvvv attribute, thus allowing them to be simplified. For <aes> the situation is slightly different: None of the remaining uses make use of vvvv anymore.
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich2-230/+261
Since {vex}/{vex3} are respected on legacy mnemonics when -msse2avx is in use, {evex} should be respected, too. So far this is the case only for insns where eGPR-s can come into play. Extend coverage to insns with only %xmm register and possibly immediate operands.
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich2-653/+1987
Legacy encoded SIMD insns are converted to AVX ones in that mode. When eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where available; there are quite a few which can't be converted). Note that LDDQU is represented as VMOVDQU32 (and the prior use of the sse3 template there needs dropping, to get the order right). Note further that in a few cases, due to the use of templates, AVX512VL is used when AVX512F would suffice. Since AVX10 is the main reference, this shouldn't be too much of a problem.
2024-05-03x86: zap value-less Disp8MemShift from non-EVEX templatesJan Beulich1-7/+19
In order to allow to continue to use templatized SSE2AVX templates when enhancing those to also cover eGPR usage, Disp8MemShift wants using to deviate from what general template attributes supply. That requires using Disp8MemShift in a way also affecting non-EVEX templates, yet having this attribute set would so far implicitly mean EVEX encoding. Recognize the case and instead zap the attribute if no other attribute indicates EVEX encoding. No change in generated tables.
2024-04-23arm: Fix MVE vmla encodingClaudio Bantaloukas1-1/+1
2024-04-22aarch64: Fix coding style issue in `aarch64-dis.c'Victor Do Nascimento1-1/+1
Fix integer value being returned from boolean function, as introduced in `aarch64: Remove asserts from operand qualifier decoders [PR31595]'.
2024-04-22x86/APX: Add invalid check for APX EVEX.X4.Cui, Lili1-0/+3
gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Added invalid check for APX X4. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added invalid testcase. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis.c (get_valid_dis386): Added invalid check for APX X4.
2024-04-19mmix disassemble memory leakAlan Modra1-0/+1
It's a once-off and of no consequence, but fix it anyway. The mmix caonoicalize_syms array is an array of pointers. Freeing it won't lose symbol names. * mmix-dis.c (initialize_mmix_dis_info): Free syms.
2024-04-17aarch64: Remove asserts from operand qualifier decoders [PR31595]Victor Do Nascimento1-18/+80
Given that the disassembler should never abort when decoding (potentially random) data, assertion statements in the `get_*reg_qualifier_from_value' function family prove problematic. Consider the random 32-bit word W, encoded in a data segment and encountered on execution of `objdump -D <obj_name>'. If: (W & ~opcode_mask) == valid instruction Then before `print_insn_aarch64_word' has a chance to report the instruction as potentially undefined, an attempt will be made to have the qualifiers for the instruction's register operands (if any) decoded. If the relevant bits do not map onto a valid qualifier for the matched instruction-like word, an abort will be triggered and the execution of objdump aborted. As this scenario is perfectly feasible and, in light of the fact that objdump must successfully decode all sections of a given object file, it is not appropriate to assert in this family of functions. Therefore, we add a new pseudo-qualifier `AARCH64_OPND_QLF_ERR' for handling invalid qualifier-associated values and re-purpose the assertion conditions in qualifier-retrieving functions to be the predicate guarding the returning of the calculated qualifier type. If the predicate fails, we return this new qualifier and allow the caller to handle the error as appropriate. As these functions are called either from within `aarch64_extract_operand' or `do_special_decoding', both of which are expected to return non-zero values, it suffices that callers return zero upon encountering `AARCH64_OPND_QLF_ERR'. Ar present the error presented in the hypothetical scenario has been encountered in `get_sreg_qualifier_from_value', but the change is made to the whole family to keep the interface consistent. Bug: https://sourceware.org/PR31595
2024-04-17Add W table for USER_MSR under MAP4.Hu, Lin14-3/+13
opcodes/ChangeLog: * i386-dis-evex-mod.h: Modify MOD_EVEX_MAP4_F8_P1, MOD_EVEX_MAP4_F8_P3. * i386-dis-evex-w.h (EVEX_W_MAP4_F8_P1_M_1): New. (EVEX_W_MAP4_F8_P3_M_1): Ditto. * i386-dis.c (vex_w_table): Add EVEX_W_MAP4_F8_P1_M_1, EVEX_W_MAP4_F8_P3_M_1. * i386-opc.tbl: Remove redundant '|'.
2024-04-09aarch64: Treat operand "SME list of ZA tiles" as immediate (PR 31561)Jens Remus1-1/+1
The AArch64 instruction table (aarch64-tbl.h) defines the operand "SME list of ZA tiles" (SME_list_of_64bit_tiles) as immediate. During assembly it is correctly encoded as immediate value (imm.value) in parse_operands. During disassembly it is first correctly decoded as immediate value (imm.value) in aarch64_ext_imm called by aarch64_extract_operand, but then erroneously treated as register number (reg.regno) in aarch64_print_operand. This resolves the assembler test case "SME extension (ZERO)" to erroneously fail on s390. On AArch64 - being little-endian - the struct aarch64_opnd_info union fields reg.regno and imm.value share their least-significant bits. On s390 - being big-endian - they do not. opcodes/ PR binutils/31561 * aarch64-opc.c: Treat operand "SME list of ZA tiles" as immediate. Bug: https://sourceware.org/PR31561 Signed-off-by: Jens Remus <jremus@linux.ibm.com> Acked-by: Nick Clifton <nickc@redhat.com>
2024-04-09s390: Flag conditional branch relative insns as condjumpJens Remus1-4/+4
Flag conditional branch relative (extended) mnemonics clij* and clgij* as "condjump" for jump visualization in disassembly. They were missed to be flagged as such in commit c5306fed7d40 ("s390: Support for jump visualization in disassembly"). opcodes/ * s390-opc.txt: Flag conditional branch relative instructions clij* and clgij* as condjump for jump visualization in disassembly. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Acked-by: Nick Clifton <nickc@redhat.com>
2024-04-09arm: Fix disassembly of MVE vq[r]shr[u]nAlex Coplan1-0/+4
This patch fixes the disassembly of vq[r]shr[u]n insns so that the shift immediate is properly decoded. See the description of the previous patch for an example of the incorrect disassembly. As part of this patch we also fix the mve-vqrshrn.d test which was testing for the incorrect disassembly of the immediates. The disassembly now matches the assembled instructions in that test. Finally we add an mve-vqshrn test which tests the non-rounding variants of those insns, whose encoding we fixed with the previous patch in this series.
2024-04-09arm: Refactor condition for print_mve_shift_nAlex Coplan1-10/+25
This is intended to have no functional change, but refactors the condition guarding the call to print_mve_shift_n in arm-dis.c ahead of a later patch which adds additional insns to the set of those whose shift immediate is disassembled using print_mve_shift_n.
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei2-0/+71
Support zcmp extension push/pop/popret and popret zero instructions. The `reg_list' is a list containing 1 to 13 registers, we can use: "{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}" to present this feature. Passed gcc/binutils regressions of riscv-gnu-toolchain. Most of work was finished by Sinan Lin. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp. (riscv_supported_std_z_ext): Added zcmp with version 1.0. (riscv_parse_check_conflicts): Zcmp conflicts with d/zcd. (riscv_multi_subset_supports): Handle zcmp. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (regno_to_reg_list): New function, used to map register to reg_list number. (reglist_lookup): Called reglist_lookup_internal. Return false if reg_list number is zero, which is an invalid value. (reglist_lookup_internal): Parse register list, and return the last register by regno_to_reg_list. (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/march-help.l: Updated. * testsuite/gas/riscv/zcmp-push-pop-fail.d: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.l: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.s: New test. * testsuite/gas/riscv/zcmp-push-pop.d: New test. * testsuite/gas/riscv/zcmp-push-pop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp. (MATCH/MASK_CM_POP): Ditto. (MATCH/MASK_CM_POPRET): Ditto. (MATCH/MASK_CM_POPRETZ): Ditto. (DECLARE_INSN): New declarations for zcmp. * opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm operand for zcmp. (OP_MASK_REG_LIST): Handle operand for zcmp register list. (OP_SH_REG_LIST): Ditto. (ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base. (X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers. (enum riscv_insn_class): Added INSN_CLASS_ZCMP. (extern riscv_get_sp_base): Added. opcodes/ChangeLog: * riscv-dis.c (print_reg_list): New function, used to get zcmp reg_list field. (riscv_get_spimm): New function, used to get zcmp sp adjustment immediate. (print_insn_args): Handle new operands for zcmp. * riscv-opc.c (riscv_get_sp_base): New function, used by gas and objdump. Get sp base adjustment. (riscv_opcodes): Added zcmp instructions.
2024-04-09Support {evex} pseudo prefix for decode evex promoted insns without egpr32.Hu, Lin12-42/+74
This patch is based on APX NF patch and also adds test cases for Checking 64-bit insns not sizeable through register operands with evex. gas/ChangeLog: * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Added no-egpr testcases for movbe. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added tests. * testsuite/gas/i386/noreg64-evex.d: New test. * testsuite/gas/i386/noreg64-evex.e: Ditto. * testsuite/gas/i386/noreg64-evex.s: Ditto. * testsuite/gas/i386/x86-64-apx_f-evex.d: Ditto. * testsuite/gas/i386/x86-64-apx_f-evex.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Added %ME to movbe. * i386-dis.c : Added %XE to evex_from_vex instructions to output {evex}. (struct dis386): New %ME. (putop): Handle %ME and output {evex} for evex_from_legacy instructions. * Return early when the instruction name is (bad).
2024-04-07Support APX NFCui, Lili7-397/+825
For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-06Revert "x86: Restore APX shift-double instructions with omitted shift count"H.J. Lu2-309/+284
This reverts commit c2d698fe03a6092d58a07de96068b87836daced0. GCC 14 has been changed to use explicit shift count in shift-double instructions by the commit: 06a7e7514af x86: Use explicit shift count in double-precision shifts gas/ PR gas/31606 * testsuite/gas/i386/x86-64-apx-ndd-wig.d: Updated. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.s: Remove tests for APX shift-double instructions with omitted shift count. opcodes/ PR gas/31606 * i386-opc.tbl: Remove APX shift-double instructions with omitted shift count. * i386-tbl.h: Regenerated.
2024-04-05Add missing install-dvi and install-ps Makefie targets.Christophe Lyon1-0/+2
For some reason, these targets are missing although others from the same family are present. This looks like an oversight. This enables calling 'make install-dvi' from the top-level build directory.
2024-04-04x86: Restore APX shift-double instructions with omitted shift countH.J. Lu2-284/+309
Restore APX shift-double instructions with omitted shift count since they are generated by GCC as shown in: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114590 gas/ PR gas/31606 * testsuite/gas/i386/x86-64-apx-ndd-wig.d: Updated. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.s: Add tests for APX shift-double instructions with omitted shift count. opcodes/ PR gas/31606 * i386-opc.tbl: Restore APX shift-double instructions with omitted shift count. * i386-tbl.h: Regenerated.
2024-04-03Arm64: check tied operand specifier in aarch64-genJan Beulich2-1/+38
Make sure that field actually matches the specified operands. Don't follow existing F_PSEUDO checking in using assertions, though. Print meaningful error messages, thus - while not having a line number available - at least providing some indication of where things are wrong. Fix SVE2.1's extq accordingly, but don't extend the testsuite there: There are further issues with its operands (SVE_Zm_imm4 doesn't look to be correct to use there, as that describes an indexed vector register, while here a separate vector register and immediate operand are to be specified).
2024-04-03x86: add missing No_qSuf to non-64-bit PTWRITEJan Beulich2-2/+2
While largely benign, it still should have been put there when the original single template was split (commit a04973848dc5).
2024-04-03x86: drop stray Size64 from WRSSQJan Beulich2-4/+4
Like for WRUSSQ it's not needed here. The legacy insn had gained it in the course of zapping Rex64, but that attribute wasn't needed here either. The APX insn then simply gained it by copy-and-paste, I suppose.
generated by cgit v1.1 at 2025-09-23 17:31:24 +0000