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2024-12-03Support Intel AVX10.2 BF16 instructionsKong Lingling6-2042/+2642
In this patch, we will support AVX10.2 BF16 instructions. All of them are new instructions forms. In current documentation, it is still VSCALEFPBF16, but it will change to VSCALEFNEPBF16 eventually. In disassembler part, we added %XB to reduce W table pass since all of them get evex.w=0. gas/Changelog: * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-bf16-intel.d: New. * testsuite/gas/i386/avx10_2-256-bf16.d: Ditto. * testsuite/gas/i386/avx10_2-256-bf16.s: Ditto. * testsuite/gas/i386/avx10_2-512-bf16-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-bf16.d: Ditto. * testsuite/gas/i386/avx10_2-512-bf16.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-bf16-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-bf16.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-bf16.s: Ditto. opcodes/ * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F. Add PREFIX_EVEX_MAP6_2C, PREFIX_EVEX_MAP6_4C, PREFIX_EVEX_MAP6_4E, PREFIX_EVEX_MAP6_98, PREFIX_EVEX_MAP6_9A, PREFIX_EVEX_MAP6_9C, PREFIX_EVEX_MAP6_9E, PREFIX_EVEX_MAP6_A8, PREFIX_EVEX_MAP6_AA, PREFIX_EVEX_MAP6_AC, PREFIX_EVEX_MAP6_AE, PREFIX_EVEX_MAP6_B8, PREFIX_EVEX_MAP6_BA, PREFIX_EVEX_MAP6_BC, PREFIX_EVEX_MAP6_BE. * i386-dis-evex.h (evex_table): Update PREFIX_EVEX_MAP6_2C, PREFIX_EVEX_MAP6_42, PREFIX_EVEX_MAP6_4C, PREFIX_EVEX_MAP6_4E, PREFIX_EVEX_MAP6_98, PREFIX_EVEX_MAP6_9A, PREFIX_EVEX_MAP6_9C, PREFIX_EVEX_MAP6_9E, PREFIX_EVEX_MAP6_A8, PREFIX_EVEX_MAP6_AA, PREFIX_EVEX_MAP6_AC, PREFIX_EVEX_MAP6_AE, PREFIX_EVEX_MAP6_B8, PREFIX_EVEX_MAP6_BA, PREFIX_EVEX_MAP6_BC, PREFIX_EVEX_MAP6_BE. * i386-dis.c (PREFIX_EVEX_MAP6_2C): New enum. (PREFIX_EVEX_MAP6_42): Ditto. (PREFIX_EVEX_MAP6_4C): Ditto. (PREFIX_EVEX_MAP6_4E): Ditto. (PREFIX_EVEX_MAP6_98): Ditto. (PREFIX_EVEX_MAP6_9A): Ditto. (PREFIX_EVEX_MAP6_9C): Ditto. (PREFIX_EVEX_MAP6_9E): Ditto. (PREFIX_EVEX_MAP6_A8): Ditto. (PREFIX_EVEX_MAP6_AA): Ditto. (PREFIX_EVEX_MAP6_AC): Ditto. (PREFIX_EVEX_MAP6_AE): Ditto. (PREFIX_EVEX_MAP6_B8): Ditto. (PREFIX_EVEX_MAP6_BA): Ditto. (PREFIX_EVEX_MAP6_BC): Ditto. (PREFIX_EVEX_MAP6_BE): Ditto. (putop): Handle %XB. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2024-12-02x86: default to not accepting MPX insnsJan Beulich2-2/+2
Gcc9 had MPX support removed. While we don't want to remove support, require these deprecated insns (and registers) to be enabled explicitly.
2024-11-29s390: Treat addressing operand sequence as one in disassemblerJens Remus1-18/+66
Reuse logic introduced with the preceding commit in the assembler to treat addressing operand sequences D(X,B), D(B), and D(L,B) as one with regards to optional last operands (i.e. optparm and optparm2). With this "nop" now disassembles into "nop" instead of "nop 0". opcodes/ * s390-dis.c (operand_count): New helper to count the remaining operands, treating D(X,B), D(B), and D(L,B) as one. (skip_optargs_p): New helper to test whether remaining operands are optional. (skip_optargs_zero_p): New helper to test whether remaining operands are optional and their values are zero. (s390_print_insn_with_opcode): Use skip_optargs_zero_p to skip optional last operands with a value of zero. gas/testsuite/ * gas/s390/zarch-optargs.d (nop): Adjust test case accordingly. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-29s390: Fix disassembly of optional addressing operandsJens Remus1-12/+22
"nop D1(B1)" erroneously disassembled into "nop D1(B1" (missing closing parenthesis). "nop D1(X1,0)" and "nop D1(X1,)" erroneously disassembled into "nop D1(X1)" (missing zero base register) instead of "nop D1(X1,0)". Do not skip disassembly of optional operands if they are index (X) or base (B) registers or length (L) in an addressing operand sequence "D(X,B)", "D(B)", or "D(L,B). Index and base register operand values of zero are being handled separately, as they may not be omitted unconditionally. For instance a base register value of zero must be printed in above mentioned case, to distinguish the index from the base register. This also ensures proper formatting of addressing operand sequences. While at it add further test cases for instructions with optional operands. opcodes/ * s390-dis.c (s390_print_insn_with_opcode): Do not unconditionally skip disassembly of optional operands with a value of zero, if within an addressing operand sequence. gas/testsuite/ * gas/s390/zarch-optargs.d: Add further test cases for instructions with optional operands. * gas/s390/zarch-optargs.s: Likewise. Reported-by: Florian Krohm <flo2030@eich-krohm.de> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-29x86: SETcc doesn't permit W suffixJan Beulich2-31/+31
Accidentally I had removed No_wSuf when cloning the extra template.
2024-11-27Re: nios2: Remove binutils support for Nios II targetAlan Modra1-2/+0
Remove a now unused config file, regenerate POTFILES to remove nios2 refs, and modify config.bfd to report the target is obsolete.
2024-11-26nios2: Remove binutils support for Nios II target.Sandra Loosemore8-1846/+0
The Nios II architecture has been EOL'ed by the vendor. This patch removes all binutils, bfd, gas, binutils, and opcodes support for this target with the exception of the readelf utility. (The ELF EM_* number remains valid and the relocation definitions from the Nios II ABI will never change in future, so retaining the readelf support seems consistent with its purpose as a utility that tries to parse the headers in any ELF file provided as an argument regardless of target.)
2024-11-24opcodes: fix Werror=format build breaker in opcodes/riscv-dis.cTom de Vries1-1/+1
I build gdb on arm-linux and ran into: ... CC riscv-dis.lo opcodes/riscv-dis.c: In function ‘print_insn_args’: opcodes/riscv-dis.c:743:29: error: format ‘%lu’ expects argument of type \ ‘long unsigned int’, but argument 4 has type ‘insn_t’ \ {aka ‘long long unsigned int’} [-Werror=format=] 743 | "%lu", EXTRACT_ZCMT_INDEX (l)); | ~~^ | | | long unsigned int | %llu ... Fix this by printing the insn_t value, which is a uint64_t, using PRIu64. Tested by finishing the build.
2024-11-22RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and ↵Nelson Chu1-0/+14
xsfvfnrclipxfqf Those SiFive extensions have been published on the web for a while, and we plan to implement intrinsics in GCC for those instructions soon. NOTE: The original patch was written by Nelson when he was still working at SiFive, and Kito rebased it to the trunk. Therefore, I kept the author as Nelson with his SiFive email. Document links: xsfvqmaccdod: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvqmaccqoq: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvfnrclipxfqf: https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2024-11-20PowerPC: Add support for RFC02677 - VSX Vector Rotate Left WordPeter Bergner1-0/+1
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvrlw. gas/ * testsuite/gas/ppc/future.s: Add test for xvrlw. * testsuite/gas/ppc/future.d: Likewise.
2024-11-20arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M MainlineAndre Vieira1-4/+27
Add support for pac_key_[pu]_[0-3](_ns)? register operands for the MRS and MSR instructions when assembling for Armv8.1-M Mainline, as well as adding the corresponding support for disassembling instructions that use it.
2024-11-20RISC-V: Add Zcmt instructions and csr.Jiawei2-0/+28
This patch supports Zcmt[1] instruction 'cm.jt' and 'cm.jalt'. Add new CSR jvt for tablejump using. Since 'cm.jt' and 'cm.jalt' have the same instructiong encoding, use 'match_cm_jt' and 'match_cm_jalt' check the 'zcmt_index' field to distinguish them. [1] https://github.com/riscvarchive/riscv-code-size-reduction/releases Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): New CSR. (riscv_csr_address): Ditto. (validate_riscv_insn): New operand. (riscv_ip): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. * testsuite/gas/riscv/zcmt-fail.d: New test. * testsuite/gas/riscv/zcmt-fail.l: New test. * testsuite/gas/riscv/zcmt-fail.s: New test. * testsuite/gas/riscv/zcmt.d: New test. * testsuite/gas/riscv/zcmt.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_JT): New opcode. (MASK_CM_JT): New mask. (MATCH_CM_JALT): New opcode. (MASK_CM_JALT): New mask. (CSR_JVT): New CSR. (DECLARE_INSN): New declaration. (DECLARE_CSR): Ditto. * opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco. (ENCODE_ZCMT_INDEX): Ditto. (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operand. * riscv-opc.c (match_cm_jt): New function. (match_cm_jalt): Ditto.
2024-11-19Support x86 Intel MSR_IMMHu, Lin16-833/+914
gas/ChangeLog: * NEWS: Support x86 Intel MSR_IMM. * config/tc-i386.c (cpu_arch): Add MSR_IMM. (cpu_flags_match): Add MSR_IMM to APX_F related processing. (i386_assemble): WRMSRNS's first operand is imm32, so add MN_wrmsrns like MN_uwrmsr. * doc/c-i386.texi: Document .msr_imm. * testsuite/gas/i386/i386.exp: Run MSR_IMM tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/msr_imm-inval.l: New test. * testsuite/gas/i386/msr_imm-inval.s: Ditto. * testsuite/gas/i386/x86-64-msr_imm-intel.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add REG_VEX_MAP7_F6_L_0_W_0, PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, VEX_LEN_MAP7_F6, VEX_W_MAP7_F6_L_0. (reg_table): New entry for MSR_IMM. (prefix_table): Ditto. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map7_f6_opcode): New variable for MAP7. (get_valid_dis386): Support MAP7. * i386-gen.c (cpu_flags): Add MSR_IMM. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumsr_imm. * i386-opc.tbl: Add MSR_IMM instructions. * i386-tbl.h: Regenerated.
2024-11-18x86: rename SPACE_{,E}VEX_MAP<N>Jan Beulich4-744/+744
Map7 already has dual purpose for USER-MSR (and is to gain more for MSR-IMM), while Map5 is about to gain VEX uses for AMX extensions. Drop the not really meaningful infixes and (in the opcode table) prefixes, retaining merely EVexMap4 for encoding EVex128 at the same time.
2024-11-18x86: VP2INTERSECT{D,Q} have mask register destination groupJan Beulich2-3/+3
Much like AVX512-{4FMAPS,4VNNIW} have a constraint on their register source, there's a constraint (need to be even) on the destination register here. Adjust "good" test cases accordingly, and add a new test case to check the warning.
2024-11-18x86: generalize "implicit quad group" handlingJan Beulich2-10/+12
We'll want to re-use it for VP2INTERSECT{D,Q}. While there add a testcase for the similarly affected AVX512-4VNNIW insns.
2024-11-18s390: Add arch15 Concurrent-Functions Facility insnsJens Remus2-0/+10
opcodes/ * s390-opc.txt: Add arch15 Concurrent-Functions Facility instructions. * s390-opc.c (INSTR_SSF_RRDRD2, MASK_SSF_RRDRD2): New SSF instruction format variant. gas/testsuite/ * gas/s390/zarch-arch15.d: Tests for arch15 Concurrent-Functions Facility instructions. * gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-18s390: Add arch15 instruction namesJens Remus1-106/+114
opcodes/ * s390-opc.txt: Add arch15 instruction names. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-18opcodes: fix -std=gnu23 compatibility wrt static_assertSam James3-3/+7
static_assert is declared in C23 so we can't reuse that identifier: * Define our own static_assert conditionally; * Rename "static assert" hacks to _N as we do already in some places to avoid a conflict. ChangeLog: PR ld/32372 * i386-gen.c (static_assert): Define conditionally. * mips-formats.h (MAPPED_INT): Rename identifier. (MAPPED_REG): Rename identifier. (OPTIONAL_MAPPED_REG): Rename identifier. * s390-opc.c (static_assert): Define conditionally.
2024-11-08aarch64: add flag OPD_F_UNSIGNED to distinguish signedness of immediate operandsMatthieu Longo2-23/+77
This patch introduces a new operand flag OPD_F_UNSIGNED to signal that the immediate value should be treated as an unsigned value. The default signedness of immediate operands is signed.
2024-11-08aarch64: improve debuggability on array of enumMatthieu Longo1-3/+3
The current space optmization on enum aarch64_opn_qualifier forced its encoding using an unsigned char. This "hard-coded" optimization has the bad consequence of making the array of such enums being completely unreadable when debugging with GDB because the enum type is lost along the way. Keeping this space optimization, and the enum type as well, is possible when the declaration of the enum is tagged with attribute((packed)). attribute((packed)) is a GNU extension, and is wrapped in the macro ATTRIBUTE_PACKED (defined in ansidecl.h), and should be used instead.
2024-11-08aarch64: change returned type to bool to match semantic of functionsMatthieu Longo2-172/+172
2024-11-08arm, objdump: print obsolote warning when 26-bit set in instructionsAndre Vieira1-25/+19
Arm has obsoleted the 26-bit addressing mode. Diagnose this when disasembling these instructions by printing OBSOLETE.
2024-11-08arm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira1-4/+23
For any arm elf target, disable an old piece of code that forced disassembly to disassemble for 'unknown architecture' which once upon a time meant it would disassemble ANY arm instruction. This is no longer true with the addition of Armv8.1-M Mainline, as there are conflicting encodings for different thumb instructions. BFD however can detect what architecture the object file was assembled for using information in the notes section. So if available, we use that, otherwise we default to the old 'unknown' behaviour. With the changes above code, a mode changing 'bx lr' assembled for armv4 with the option --fix-v4bx will result in an object file that is recognized by bfd as one for the armv4 architecture. The disassembler now disassembles this encoding as a BX even for Armv4 architectures, but warns the user when disassembling for Armv4 that this instruction is only valid from Armv4T onwards. Remove the unused and wrongfully defined ARM_ARCH_V8A_CRC, and define and use a ARM_ARCH_V8R_CRC to make sure instructions enabled by -march=armv8-r+crc are disassembled correctly. Patch up some of the tests cases, see a brief explanation for each below. inst.d: This test checks the assembly & disassembly of basic instructions in armv3m. I changed the expected behaviour for teqp, cmnp cmpp and testp instructions to properly print p when disassembling, whereas before, in the 'unknown' case it would disassemble these as UNPREDICTABLE as they were changed in later architectures. nops.d: Was missing an -march, added one to make sure we were testing the right behavior of NOP<c> instructions. unpredictable.d: Was missing an -march, added armv6 as that reproduced the behaviour being tested.
2024-10-31RISC-V: Dump instruction without checking architecture support as usual.Nelson Chu1-1/+7
Since QEMU have supported -Max option to to enable all normal extensions, the dis-assembler should also add an option, -M,max to do the same thing. For the instruction, which have overlapped encodings like zfinx, will not be considered by the -M,max option. opcodes/ * riscv-dis.c (all_ext): New static boolean. If set, disassemble without checking architectire string. (riscv_disassemble_insn): Likewise. (parse_riscv_dis_option_without_args): Recognized -M,max option. binutils/ * NEWS: Updated.
2024-10-30x86/APX: support JMPABS also in assemblerJan Beulich3-903/+924
Without this APX support isn't really complete. For Intel syntax displacement form is needed, such that symbolic operands won't need prefixing by "offset". (The other form is actually not used at all in Intel syntax.) For the record: To restrict displacement form to Intel syntax is not something I actually agree with.
2024-10-29x86: use <xyz> for VFPCLASSP{S,D}Jan Beulich2-35/+31
Just like VFPCLASSPH does. While the order of generated table entries changes this way, the individual entries don't change.
2024-10-18x86: Regenerate missing table filesMayShao-oc3-4388/+4428
As soon as I committed Zhaoxin's patch, I realized that I did not include the regen file. Regenerate them and commit as obvious. opcodes/ChangeLog: * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc4-1/+56
gas/ChangeLog: * NEWS: Support ZHAOXIN GMI instructions. * config/tc-i386.c: Add gmi. * doc/c-i386.texi: Document gmi. * testsuite/gas/i386/i386.exp: Add gmi test. * testsuite/gas/i386/gmi.d: Ditto. * testsuite/gas/i386/gmi.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New comment. * i386-gen.c: Add gmi. * i386-opc.h (CpuGMI): New. * i386-opc.tbl: Add Zhaoxin GMI instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2024-10-16Support Intel AVX10.2 convert instructionsLiwei Xu6-1996/+2488
In this patch, we will support AVX10.2 convert instructions. All of them are new instruction forms. Among all the instructions, vcvtbiasph2[b,h]f8[,s] needs extra care. Since Operand 2 could indicate memory size, we do not need suffix under ATTmode. However, we could not fold all three templates but only XMM/YMM since the dst operand size are the same for them. Also, a new iterator <cvt8> is added to reduce redundancy. gas/ * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-cvt-intel.d: New. * testsuite/gas/i386/avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.s: Ditto. opcodes/ * i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F3874, PREFIX_EVEX_MAP5_18, PREFIX_EVEX_MAP5_1B, PREFIX_EVEX_MAP5_1E and PREFIX_EVEX_MAP5_74. * i386-dis-evex.h: Add table pass for AVX10.2 instructions. * i386-dis.c (MOD_EVEX_0F38B1): New. (PREFIX_EVEX_0F3874): Ditto. (PREFIX_EVEX_MAP5_18): Ditto. (PREFIX_EVEX_MAP5_1B): Ditto. (PREFIX_EVEX_MAP5_1E): Ditto. (PREFIX_EVEX_MAP5_74): Ditto. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Kong Lingling <lingling.kong@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2024-10-14x86: also template-expand trailing mnemonic partJan Beulich1-60/+72
So far template expansion was limited to fields other than the insn mnemonic. In order to be able to use <fop> also for AVX10.2 we want the trailing mnemonic part to also be expanded. Split out the respective piece of code into a helper function, which is then invoked twice.
2024-10-14LoongArch: Fixed R_LARCH_[32/64]_PCREL generation bugLulu Cai1-1/+2
The enum BFD_RELOC_[32/64] was mistakenly used in the macro instead of the relocation in fixp. This can cause the second relocation of a pair to be deleted when -mthin-add-sub is enabled. Apply the correct macro to fix this. Also sets the initial value of -mthin-add-sub.
2024-10-11Support Intel AVX10.2 media instructionsHaochen Jiang7-702/+893
In disassembler part, for vnni instructions, we extended previous VEX part using %XE in disassembler to promote them to EVEX by reusing the original VEX table. For vmpsadbw, we will also use %XE. However, it is hard to reuse the VEX table, so we are using new ones. In assmbler part, we put the vnni table entries with previous vnni instructions since they are just promotion from AVX-VNNI-INT{8,16}. Since we will prefer VEX encoding, we need to use the different table order in template <vnni>, which prefers EVEX due to earlier introduction for AVX512_VNNI than AVX_VNNI. This means a new <vnni>. For vdpphps and vmpsadbw, we put them at the end of the table, with future AVX10.2 instructions. Nit: I will remove the arch requirement for avx_vnni_int{8,16} in evex-promote testcases after AVX10.2 implies AVX-VNNI-INT{8,16}. gas/Changelog: * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-1-intel.d: New. * testsuite/gas/i386/avx10_2-256-1.d: Ditto. * testsuite/gas/i386/avx10_2-256-1.s: Ditto. * testsuite/gas/i386/avx10_2-512-1-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-1.d: Ditto. * testsuite/gas/i386/avx10_2-512-1.s: Ditto. * testsuite/gas/i386/avx10_2-promote.d: Ditto. * testsuite/gas/i386/avx10_2-promote.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-promote.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-promote.s: Ditto. opcodes/Changelog: * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F3852. Add PREFIX_EVEX_0F3A42_W_0. * i386-dis-evex-w.h: Adjust EVEX_W_0F3A42. * i386-dis-evex.h: Add table pass for AVX10.2 instructions. * i386-dis.c: Adjust PREFIX_VEX_0F3850_W_0, PREFIX_VEX_0F3851_W_0, PREFIX_VEX_0F38D2_W_0 and PREFIX_VEX_0F38D3_W_0. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Lili Cui <lili.cui@intel.com>
2024-10-10s390: Add arch15 instructionsAndreas Krebbel3-3/+127
opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
2024-10-07m68k: Support for jump visualization in disassemblyAndreas Schwab1-0/+27
opcodes/ * m68k-dis.c (m68k_opcode_to_insn_type): Define. (match_insn_m68k): Call it to set insn_type. (print_insn_arg) [case 'B']: Set branch target address. (print_insn_m68k): Set insn_info_valid.
2024-09-27RISC-V: correct alignment directive handling for text sectionsJan Beulich1-1/+1
.insn or data emitted inside text sections can lead to positions not being at insn granularity. In such situations using alignment directives should reliably enforce the requested alignment. Specifically requests to align back to insn granularity may not be ignored (where, as a subcase thereof, the ordering of ".option norvc" and e.g. ".p2align 2" should not matter; so far the alignment directive needs to come first to have any effect). Similarly ahead of emitting NOPs alignment first needs to be forced back to insn granularity. The new testcases actually point out a corner case issue in the disassembler as well, which is being corrected at the same time: We don't want to print "0x" without any subsequent digits.
2024-09-27x86: optimize {,V}INSERTPS with certain immediatesJan Beulich2-7/+7
They are equivalent to simple moves or xors, which are up to 3 bytes shorter to encode (and maybe/likely also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0Jan Beulich2-20/+20
They, too, are equivalent to simple moves, which are up to 3 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACTPS with immediate 0Jan Beulich2-12/+12
They are equivalent to simple moves, which are up to 2 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-26x86: templatize SIMD narrowing-move templatesJan Beulich2-72/+32
Once again to reduce redundancy.
2024-09-26x86: templatize SIMD sign-/zero-extension templatesJan Beulich2-251/+220
Yet again to reduce redundancy.
2024-09-26x86: templatize SIMD FP binary-logic templatesJan Beulich2-282/+271
Once more to reduce redundancy.
2024-09-26x86: further templatize FMA templatesJan Beulich2-349/+339
Further reduce redundancy, in preparation of the addition of counterparts for AVX10.2.
2024-09-26x86: templatize SIMD FP arithmetic templatesJan Beulich2-1135/+1100
Reduce redundancy, in preparation of the addition of further counterparts for AVX10.2. Provide the "ne" parameter needed there right away, even if unused for now.
2024-09-18x86/APX: Don't promote AVX/AVX2 instructions out of APX specH.J. Lu2-337/+197
V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} aren't promoted to support EGPR in APX spec. Don't promote them out of APX spec. This commit effectively reverted: ec3babb8c10 x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed 5a635f1f59a x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL} eea4357967b x86/APX: VROUND{P,S}{S,D} can generally be encoded gas/ PR gas/32171 * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Add V{BROADCAST,EXTRACT,INSERT}{F,I}128 tests with EGPR. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} tests with EGPR. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: Updated. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Likewise. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise. opcodes/ PR gas/32171 * i386-opc.tbl: Remove V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} entries with EGPR. * i386-tbl.h: Regenerated. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-12s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraintsJens Remus1-15/+9
This leverages commit ("s390: Simplify (dis)assembly of insn operands with const bits") to relax the operand constraints of the immediate operand that contains the constant Z- or T-bit of the following extended mnemonics: risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt Previously those instructions were the only ones where the assembler on s390 restricted the specification of the subject I3/I4 operand values exactly according to their specification to an unsigned 6- or 5-bit unsigned integer. For any other instructions the assembler allows to specify any operand value allowed by the instruction format, regardless of whether the instruction specification is more restrictive. Allow to specify the subject I3/I4 operand as unsigned 8-bit integer with the constant operand bits being ORed during assembly. Relax the instructions subject significant operand bit masks to only consider the Z/T-bit as significant, so that the instructions get disassembled as their *z or *t flavor regardless of whether any reserved bits are set in addition to the Z/T-bit. Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set the T-bit in operand I3, as they otherwise get disassembled as their rnsbgt, rosbgt, and rxsbgt counterpart. This aligns GNU Assembler to LLVM Assembler. opcodes/ * s390-opc.c (U6_18, U5_27, U6_26): Remove. (INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define as INSTR_RIE_RRUUU while retaining insn fmt mask. (MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only Z/T-bit of I3/I4 operand as significant. gas/testsuite/ * gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit. Reported-by: Dominik Steenken <dost@de.ibm.com> Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-12s390: Simplify (dis)assembly of insn operands with const bitsJens Remus2-23/+17
Simplify assembly and disassembly of extended mnemonics with operands with constant ORed bits: Their instruction template already contains the respective constant operand bits, as they are significant to distinguish the extended from their base mnemonic. Operands are ORed into the instruction template. Therefore it is not necessary to OR the constant bits into the operand value during assembly in s390_insert_operand. Additionally the constant operand bits from the instruction template can be used to mask them from the operand value during disassembly in s390_print_insn_with_opcode. For now do so for non-length unsigned integer operands only. The separate instruction formats need to be retained, as their masks differ, which is relevant during disassembly to distinguish the base and extended mnemonics from each other. This affects the following extended mnemonics: - vfaebs, vfaehs, vfaefs - vfaezb, vfaezh, vfaezf - vfaezbs, vfaezhs, vfaezfs - vstrcbs, vstrchs, vstrcfs - vstrczb, vstrczh, vstrczf - vstrczbs, vstrczhs, vstrczfs - wcefb, wcdgb - wcelfb, wcdlgb - wcfeb, wcgdb - wclfeb, wclgdb - wfisb, wfidb, wfixb - wledb, wflrd, wflrx include/ * opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2, S390_OPERAND_OR8): Remove. opcodes/ * s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove. (INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask. (INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining respective insn fmt mask. (INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3): Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt mask. * s390-dis.c (s390_print_insn_with_opcode): Mask constant operand bits set in insn template of non-length unsigned integer operands. gas/ * config/tc-s390.c (s390_insert_operand): Do not OR constant operand value bits. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-11x86/APX: correct disassembly for EVEX.B4Jan Beulich1-2/+3
EVEX.B4 is used only for GPR (or addressing of memory) operands. SIMD registers encoded via ModR/M.rm (when ModR/M.mod == 3) have their top bit in EVEX.X3. Supposedly (doc version 004) EVEX.B4 is ignored when unused, hence also don't flag such encodings as invalid.
2024-09-09s390: Align opcodes to lower-caseJens Remus1-1/+1
opcodes/ * s390-opc.txt (rdp): Change opcode to lower-case. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-06x86/APX: use D for 2-operand CFCMOVccJan Beulich2-577/+276
There's no need to have 30 redundant templates when we can easily take care of the operand swapping like we do for various other insns.
generated by cgit v1.1 at 2025-09-23 05:06:30 +0000