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2025-01-31x86: RMPUPDATE wants operands in different formJan Beulich3-51/+68
AMD are about to update their doc, to help clarify that what we currently do isn't quite right: In particular it is not %rax but %rcx which is affected by address size. In fact, that's a normal memory operand, just not expressed via ModR/M byte, but fixed to (%rcx) (or (%ecx) with 32-bit addressing). To support this in the assembler, generalize memory operand handling so far specific to XLAT (which isn't really a string insn, but requires its memory operand to be (%bx) / (%ebx) / (%rbx)). In the disassembler mimic handling after XLAT's, too.
2025-01-31x86-64: omit "default" segment prefixes from string insn disassemblyJan Beulich1-5/+8
Printing implicit %ds: and %es: prefixes is pretty meaningless in 64-bit mode. The SDM explicitly omits them for the 64-bit forms, and it obviously has them for the other ones only to cover non-64-bit modes (oddly enough the AMD PM has them present).
2025-01-27MicroBlaze: Widen mask used in opcodes/microblaze-dis,cMichael J. Eager1-8/+8
Instead of using 0xFFFF0000, or with (~0xFFFF) to sign extend negative 16-bit value and with (~0xFFFF) to extract higher order address bits opcodes/ * microblaze-dis.c: (print_insn_microblaze): Widen mask (microblaze_get_target_address): Likewis Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2025-01-27s390: Do not omit vector index register 0 in disassemblyJens Remus1-8/+5
Vector index registers are currently only used in the VRV instruction format. Unlike general purpose index registers an operand value of zero (e.g. %v0, 0, or omitted) does not imply a zero value: "For VRV format instructions, a vector element is used in the formation of the intermediate value. This vector element is an unsigned binary integer value that is added to the base address and 12-bit displacement to form a 64-bit intermediate sum. The vector element is designated by a vector register and an element index. A zero V field accesses the element in vector register zero and does not imply a zero value." [1] Therefore do not omit vector index register 0 in disassembly, that is disassemble D(VX,B) with VX=0 as D(VX,B) instead of D(B). Also do not disassemble index register 0 as "0", that is disassemble D(VX,B) with VX=0 as D(%v0,B) instead of D(0,B). Note that a base register 0 still still gets disassembled as "0", that is D(VX,B) with B=0 disassembles into D(VX,0). [1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16, https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf opcodes/ * s390-dis.c (s390_print_insn_with_opcode): Do not omit vector index register 0 in disassembly. Disassemble it as %v0. gas/testsuite/ * gas/s390/zarch-base-index-0.d (vgef): Expect vector index register 0 in disassembly. * gas/s390/zarch-omitted-base-index.d (vgef): Likewise. Suggested-by: Florian Krohm <flo2030@eich-krohm.de> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-01-23PowerPC: Add support for RFC02657 - AES acceleration instructionsSurya Kumari Jangala1-1/+79
opcodes/ * ppc-opc.c (insert_m2, extract_m2): New functions. (AESM, PGF1, XX2M, XX3M, XX3GF, XX2AES_MASK, XX2AESM_MASK, XX3AES_MASK, XX3AESM_MASK, XX3GF_MASK): New macros. (UIM): Update for new macros. (powerpc_opcodes): Add xxaes128encp, xxaes192encp, xxaes256encp, xxaesencp, xxaes128decp, xxaes192decp, xxaes256decp, xxaesdecp, xxaes128genlkp, xxaes192genlkp, xxaes256genlkp, xxaesgenlkp, xxgfmul128gcm, xxgfmul128xts, xxgfmul128. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2025-01-20Update translations for various sub-directoriesNick Clifton3-496/+497
2025-01-19Change version to 2.44.50 and regenerate filesNick Clifton2-170/+159
2025-01-19Add markers for bihnutils 2.44 branchNick Clifton1-0/+4
2025-01-17aarch64: Fix sve2p1 gating and add missing instructionsAndrew Carlotti2-333/+457
Many FEAT_SVE2p1 instructions need to be enabled by either of two different features (one for streaming mode, and one for non-streaming mode). This patch adds correct gating conditions for these instructions. There were also a few sve2p1 instructions missing altogether, so add those as well. The testsuite is modified to check for all alternative enablement conditions. In many cases this is done by adding an alternative assembler commands to existing test files. For some SME/SME2 tests, only some of the instructions are enabled by +sve2p1, so these are copied into a separate test. For original SVE2p1 tests, the non-SME2p1 instructions have been moved to a separate test file. There are also new tests for the newly added instructions. These include a couple of fixme comments relating to bad error reporting, which should be investigated later.
2025-01-17x86: Add CpuGMISM2 and CpuGMICCSMayShao-oc5-2310/+2326
There are separate CPUID feature bits for SM2 and CCS instructions. CCS is the acronym of Chinese Cipher System, it includes SM3 and SM4 instructions. This patch adds CpuGMISM2 and CpuGMICCS to replace CpuGMI on corresponding instructions. gas/ChangeLog: * config/tc-i386.c: Add gmism2 and gmiccs to replace gmi. * doc/c-i386.texi: Ditto. opcodes/ChangeLog: * i386-gen.c: Add GMISM2 and GMICCS to replace GMI. * i386-opc.h (enum i386_cpu): Add CpuGMISM2 and CpuGMICCS to replace CpuGMI. * i386-opc.tbl: Replace GMI with GMISM2 on sm2 instruction. Replace GMI with GMICCS on sm3 and sm4 instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-17x86/APX: convert runtime special case to build-time oneJan Beulich2-4/+18
cpu_flags_match() is a hot path. Move the special casing that b7267244a355 ("Support Intel AMX-MOVRS") added there to i386-gen, thus affecting only build time performance.
2025-01-17RISC-V: Use t2 for tail if Zicfilp enabledKito Cheng1-0/+1
This change is to make tail conform with software guarded jump of Zicfilp. The reason to not choose t1 as the label register is that t1 is also as .got.plt offset of _dl_runtime_resolve in PLT. See more: https://github.com/riscv-non-isa/riscv-asm-manual/pull/93
2025-01-17RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.Monk Chiang1-0/+45
https://github.com/riscv/riscv-cfi/releases/tag/v1.0 This patch only support the CFI instructions and CSR in assembler.
2025-01-17RISC-V: Support ssctr/smctr extensions with version 1.0.Nelson Chu1-2/+3
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0 The privileged spec v1.10 already removed the sfence.vm instruction, and the encoding of sfence.vm instruction is overlapped with the sctrclr instruction of ssctr/smctr. But since the privileged spec v1.10 already removed the sfence.vm, and we no longer support the privileged spec v1.9.1 for now, we had to remove the sfence.vm. bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Imply zicsr for ssctr/smctr. (riscv_supported_std_s_ext): Added ssctr/smctr with version 1.0. (riscv_multi_subset_supports): Handle INSN_CLASS for ssctr/smctr. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (enum riscv_csr_class, riscv_csr_address): Added and handle CSR_CLASS_SSCTR and CSR_CLASS_SMCTR. (riscv_is_priv_insn): Removed SFENCE_VM check. * testsuite/gas/riscv/attribute-14e.d: Removed since sfence.vm is no longer supported since privileged spec v1.10. * testsuite/gas/riscv/attribute-14.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated for ssctr/smctr CSRs. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr.s: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/march-help.l: Updated for ssctr/smctr. * testsuite/gas/riscv/smctr-ssctr.d: New testcase for sctr instruction. * testsuite/gas/riscv/smctr-ssctr.s: Likewise. include/ * opcode/riscv-opc.h: Added encoding macro for sctrclr, but removed encoding macro for sfence.vm since encoding conflict. Added CSR numbers for ssctr/smctr CSRs. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SMCTR_OR_SSCTR for sctrclr. opcodes/ * riscv-opc.c (riscv_opcodes): Added sctrclr, but removed sfence.vm since encoding conflict.
2025-01-17x86: Ignore rounding for vcvt[,u]si2sd under r32 and vcvt[,u]dq2pd instead ↵Haochen Jiang2-4/+3
of reporting bad for disassembler According to SDM, vcvt[,u]si2sd under r32 and vcvt[,u]dq2pd treat Rounding as Ignored when trying to using them. Thus, disassembler should accept bytecode with rounding instead of reporting bad. For assembler, it needs some more time to decide how to deal with that. gas/ChangeLog: * testsuite/gas/i386/evex.d: Add new testcase for vcvt[,u]dq2pd. Change the output for vcvt[,u]si2sd. * testsuite/gas/i386/evex.s: Ditto. * testsuite/gas/i386/x86-64-evex.d: Ditto. opcodes/ChangeLog: * i386-dis-evex-w.h: Add EXxEVexR64 for vcvt[,u]dq2pd. * i386-dis.c (OP_Rounding): Mark EVEX_b as used to change the handle for ignored rounding.
2025-01-16x86: Support x86 Zhaoxin PadLock PHE2 instructionsMayShao-oc7-4496/+4546
The CPUID EDX bit[26] indicates its enablement, and it includes REP XSHA384 and REP XSHA512. gas/ChangeLog: * NEWS: Support Zhaoxin PadLock PHE2 instructions. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLockPHE2 instructions. (output_insn): Handle PadLockPHE2 instructions. * doc/c-i386.texi: Document PadLockPHE2. * testsuite/gas/i386/i386.exp: Add PadLockPHE2 test. * testsuite/gas/i386/padlock_phe2.d: Ditto. * testsuite/gas/i386/padlock_phe2.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockPHE2. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockPHE2): New. * i386-opc.tbl: Add Zhaoxin PadLock PHE2 instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-16disassemble_free_powerpcAlan Modra3-0/+12
This fixes leaks in a ppc disassembler buffer. I'm not sure now why I used a private buffer for section contents, but I'm not going to change that just now. * disassemble.h (disassemble_free_powerpc): Declare. * disassemble.c (disassemble_free_target): Call it. * ppc-dis.c (disassemble_free_powerpc): New function.
2025-01-14x86: Remove "NE" in mnemonics for convert insns related to AI data typesHaochen Jiang4-2133/+2133
NE is quite ambiguous and misleading in mnemonics since it should be Rounding to Nearest Even, but could be mis-interpretated to No Exception. Under its correct meaning, which means rounding, it should only be used in down-convert, since up-convert is always exact for normal values It could be difficult to judge which kind of convert it is if we have the convert between same bit float types. For all AI data types including BF16 and FP8, the default rounding is Rounding to Nearest Even. So removing them in mnemonics would reduce burden for programmers to consider whether it should be added or not in mnemonics and stop the ambiguous meaning on "NE" itself. If the convert itself is using a rounding mode other than RNE, it would be explicitly added in mnemonics (e.g., Long used "T" and "BIAS" introduced in AVX10.2). gas/ChangeLog: * testsuite/gas/i386/avx10_2-256-cvt-intel.d: Refine testcases according to mnemonics change. * testsuite/gas/i386/avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.s: Ditto. * testsuite/gas/i386/avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.s: Ditto. * testsuite/gas/i386/avx10_2-512-satcvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-512-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Remove ne in mnemonics for convert insns. * i386-opc.tbl: Ditto. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto.
2025-01-14x86: Rename VCOMSBF16 to VCOMISBF16Haochen Jiang4-2102/+2102
The functionality for VCOMSBF16 is exactly the same as the VCOMISD/S/H. The only difference is the bf16 type. Thus, it should be VCOMISBF16. This patch would fix that. gas/ChangeLog: * testsuite/gas/i386/avx10_2-256-bf16-intel.d: Refine testcase according to mnemonics change. * testsuite/gas/i386/avx10_2-256-bf16.d: Ditto. * testsuite/gas/i386/avx10_2-256-bf16.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Rename VCOMSBF16 to VCOMISBF16. * i386-opc.tbl: Ditto. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto.
2025-01-14x86: Remove "P" and "NE" in mnemonics for BF16 arithmetic insnsHaochen Jiang4-2238/+2238
Since the bf16 is an AI data types, it will be implicitly packed. Thus, "P" (for packed) is omitted in mnemonics from its introduction. AVX10.2 BF16 arithmetic insns are introduced with "P" in mnemonics with packed. This patch will remove them for consistency. NE is quite ambiguous and misleading in mnemonics since it should be Rounding to Nearest Even, but could be mis-interpretated to No Exception. While AI data types like BF16 and FP8 are using Rounding to Nearest Even as default rounding modes. There is no need to use the ambiguous mnemonics in AVX10.2 insns. This patch will also remove them. For convert insns, it will be handled in the upcoming patch. gas/ChangeLog: * testsuite/gas/i386/avx10_2-256-bf16-intel.d: Refine testcase according to new mnemonics. * testsuite/gas/i386/avx10_2-256-bf16.d: Ditto. * testsuite/gas/i386/avx10_2-256-bf16.s: Ditto. * testsuite/gas/i386/avx10_2-256-miscs-intel.d: Ditto. * testsuite/gas/i386/avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/avx10_2-512-bf16-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-bf16.d: Ditto. * testsuite/gas/i386/avx10_2-512-bf16.s: Ditto. * testsuite/gas/i386/avx10_2-512-miscs-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-miscs.d: Ditto. * testsuite/gas/i386/avx10_2-512-miscs.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-bf16-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-bf16.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-bf16.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-miscs-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-miscs.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-miscs.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Remove p and ne in bf16 mnemonics. * i386-opc.tbl: Ditto. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto.
2025-01-14Support Intel AMX-AVX512Haochen Jiang12-1787/+2078
This patch will support AMX-AVX512. In disassmbler, we pull out all GPR mode out of the vex length switch to make it more general. gas/ChangeLog: * NEWS: Mention the full support on DMR AMX ISAs. * config/tc-i386.c: Add amx_avx512. * doc/c-i386.texi: Document .amx_avx512. * testsuite/gas/i386/x86-64.exp: Run AMX-AVX512 tests. * testsuite/gas/i386/x86-64-amx-avx512-intel.d: New test. * testsuite/gas/i386/x86-64-amx-avx512.d: Ditto. * testsuite/gas/i386/x86-64-amx-avx512.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-len.h: Add EVEX_LEN_0F384A_X86_64_W_0, EVEX_LEN_0F386D_X86_64_W_0, EVEX_LEN_0F3A07_X86_64_W_0, EVEX_LEN_0F3A77_X86_64_W_0. * i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F384A_W_0_L_2, PREFIX_EVEX_0F386D_W_0_L_2, PREFIX_EVEX_0F3A07_W_0_L_2, PREFIX_EVEX_0F3A77_W_0_L_2. * i386-dis-evex-w.h: Add EVEX_W_0F384A_X86_64, EVEX_W_0F386D_X86_64, EVEX_W_0F3A07_X86_64, EVEX_W_0F3A77_X86_64. * i386-dis-evex-x86-64.h: Add X86_64_EVEX_0F384A, X86_64_EVEX_0F386D, X86_64_EVEX_0F3A07, X86_64_EVEX_0F3A77. * i386-dis-evex.h: Ditto. * i386-dis.c (EVEX_LEN_0F384A_X86_64_W_0): New. (EVEX_LEN_0F386D_X86_64_W_0): Ditto. (EVEX_LEN_0F3A07_X86_64_W_0): Ditto. (EVEX_LEN_0F3A77_X86_64_W_0): Ditto. (MOD_EVEX_0F384A_X86_64_W_0): Ditto. (MOD_EVEX_0F386D_X86_64_W_0): Ditto. (MOD_EVEX_0F3A07_X86_64_W_0): Ditto. (MOD_EVEX_0F3A77_X86_64_W_0): Ditto. (PREFIX_EVEX_0F384A_W_0_L_2): Ditto. (PREFIX_EVEX_0F386D_W_0_L_2): Ditto. (PREFIX_EVEX_0F3A07_W_0_L_2): Ditto. (PREFIX_EVEX_0F3A77_W_0_L_2): Ditto. (EVEX_W_0F384A_X86_64): Ditto. (EVEX_W_0F386D_X86_64): Ditto. (EVEX_W_0F3A07_X86_64): Ditto. (EVEX_W_0F3A77_X86_64): Ditto. (X86_64_EVEX_0F384A): Ditto. (X86_64_EVEX_0F386D): Ditto. (X86_64_EVEX_0F3A07): Ditto. (X86_64_EVEX_0F3A77): Ditto. (OP_VEX): Pull out all GPR mode out of the vector length switch. * i386-gen.c (isa_dependencies): Add AMX-AVX512. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_AVX512): New. (i386_cpu_flags): Add cpuamx_avx512. * i386-opc.tbl: Add AMX-AVX512 instructions. * i386-tbl.h: Regenerated.
2025-01-14Support Intel AMX-MOVRSHu, Lin111-2622/+2830
This patch will support AMX-MOVRS feature. Unlike all the other AMX insns in vector space where we pass vex_len_table before vex_w_table, we first pass vex_w_table for tileloaddrs[,t1] to align with the order in EVEX space. The reason why we first pass vex_w_table in EVEX space is due to AMX-AVX512, where tcvtrowd2ps and tilemovrow with r32 shares the same opcode with tileloaddrs[,t1]. All of them have evex.w = 0 but with different evex.length. Re-doing that shortly is not ideal. APX_F extension is also implemented in this patch. The encoding will be: - EVEX.128.NP/66.MAP5.W0 F8/F9 !(11):rrr:100 for T2RPNTLVW[Z0,Z1]RS[,T1] with NF=0. - EVEX.128.F2/66.0F38.W0 4A !(11):rrr:100 FOR TILELOADDRS[,T1] with NF=0. For APX_F extension, we could not use APX_F(AMX_TRANSPOSE&AMX_MOVRS) since the transformation could not be done. Instead, we will use AMX_TRANSPOSE & APX_F(AMX_MOVRS). Thus, we should set AMX_TRANSPOSE for "any" for cpu_flags in assembler. Since it will only affect the cpu_flags_match, handle that there. gas/ChangeLog: * config/tc-i386.c (cpu_arch): Add amx_movrs. (cpu_flags_match): Set any bitfield for multiple cpuid enabled insns. * doc/c-i386.texi: Document .amx_movrs. * testsuite/gas/i386/x86-64.exp: Run AMX-MOVRS tests. * testsuite/gas/i386/x86-64-amx-movrs-intel.d: New test. * testsuite/gas/i386/x86-64-amx-movrs-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-movrs-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.d: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-len.h (EVEX_LEN_0F384A_X86_64_W_0): New. * i386-dis-evex-w.h (EVEX_W_0F384A_X86_64): Ditto. * i386-dis-evex-x86-64.h (X86_64_EVEX_0F384A): Ditto. * i386-dis-evex.h: New entry for AMX-MOVRS. * i386-dis.c: (PREFIX_VEX_0F384A_X86_64_L_0_W_0): New. (PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0): Ditto. (PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0): Ditto. (X86_64_VEX_0F384A): Ditto. (X86_64_VEX_MAP5_F8): Ditto. (X86_64_VEX_MAP5_F9): Ditto. (X86_64_EVEX_0F384A): Ditto. (VEX_LEN_0F384A_X86_64_W_0): Ditto. (VEX_LEN_MAP5_F8_X86_64): Ditto. (VEX_LEN_MAP5_F9_X86_64): Ditto. (EVEX_LEN_0F384A_X86_64_W_0): Ditto. (VEX_W_0F384A_X86_64): Ditto. (VEX_W_MAP5_F8_X86_64): Ditto. (VEX_W_MAP5_F9_X86_64): Ditto. (EVEX_W_0F384A_X86_64): Ditto. (prefix_table): New entry for AMX-MOVRS. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map5_f8_opcode): New. (map5_f9_opcode): Ditto. (get_valid_dis386): Handle VEX_MAP5 opcode for AMX-MOVRS. * i386-gen.c (isa_dependencies): Add AMX_MOVRS. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_MOVRS): New. (i386_cpu_flags): Add cpuamx_movrs. * i386-opc.tbl: Add AMX-MOVRS instructions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2025-01-14Support Intel MOVRSHu, Lin110-2649/+2792
This patch focus on supporting MOVRS ISA. We could take this full ISA as four part: PREFETCHRST2, MOVRS, MOVRS APX_F extension and MOVRS AVX10.2 extension. The APX_F extension for MOVRS will be: - EVEX.LLZ.NP.MAP4.WIG 8A !(11):rrr:bbb for r8/m8 with NF=0 and ND=0 - EVEX.LLZ.NP/66.MAP4.SCALABLE 8B !(11):rrr:bbb for rv/mv with NF=0 and ND=0 We did not merge the table together for APX_F since there is an explicit x64 for movrs insn. The current APX_F() did not support the combination between CPUIDs. Also, the space is different for legacy and apx_f forms. gas/ChangeLog: * NEWS: Support Intel MOVRS. * config/tc-i386.c: Add MOVRS. * doc/c-i386.texi: Document .movrs. * testsuite/gas/i386/i386.exp: Run MOVRS tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Add MOVRS tests. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. * testsuite/gas/i386/lfence-load.d: Add prefetchrst2. * testsuite/gas/i386/lfence-load.s: Ditto. * testsuite/gas/i386/nops-8.d: Ditto. * testsuite/gas/i386/prefetch-intel.d: Ditto. * testsuite/gas/i386/prefetch.d: Ditto. * testsuite/gas/i386/x86-64-lfence-load.d: Ditto. * testsuite/gas/i386/x86-64-lfence-load.s: Ditto. * testsuite/gas/i386/x86-64-prefetch-intel.d: Ditto. * testsuite/gas/i386/x86-64-prefetch.d: Ditto. * testsuite/gas/i386/movrs-intel.d: New test. * testsuite/gas/i386/movrs-inval.l: Ditto. * testsuite/gas/i386/movrs-inval.s: Ditto. * testsuite/gas/i386/movrs.d: Ditto. * testsuite/gas/i386/movrs.s: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256.s: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512.s: Ditto. * testsuite/gas/i386/x86-64-movrs-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs.d: Ditto. * testsuite/gas/i386/x86-64-movrs.s: Ditto. * testsuite/gas/i386/x86-64-movrs-intel-suffix.d: Ditto. * testsuite/gas/i386/x86-64-movrs-suffix.d: Ditto. * testsuite/gas/i386/x86-64-movrs-suffix.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP5_6F_X86_64. * i386-dis-evex-x86.h: Add X86_64_EVEX_MAP5_6F. * i386-dis-evex.h (evex_table): New entry for movrs. * i386-dis.c (MOD_0F18_REG_4): New. (PREFIX_EVEX_MAP5_6F_X86_64): Ditto. (X86_64_0F388A): Ditto. (X86_64_0F388B): Ditto. (X86_64_EVEX_MAP5_6F): Ditto. (three_byte_table): New entry for MOVRS. (reg_table): Ditto. (mod_table): Ditto. (x86_64_table): Ditto. Also include i386-dis-evex-x86.h. * i386-gen.c (cpu_flags): Add MOVRS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumovrs. * i386-opc.tbl: Add MOVRS instrctions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> Co-authored-by: Lili Cui <lili.cui@intel.com>
2025-01-14x86: Remove mod_table pass for MVexSIBMEMHaochen Jiang1-28/+18
When using MVexSIBMEM, OP_M will help check modrm. Thus, no need to pass mod_table. Since we have OP_M do the work, from now on, mod_table[] should not gain any new entries, unless both slots of them are populated, e.g., different modrm leading to different insns could not be combined (Bad_Opcode is not the case since OP_M could handle that). opcodes/ChangeLog: * i386-dis.c: Remove mod_table pass for MVexSIBMEM.
2025-01-10aarch64: Add support for FEAT_SME_B16B16 feature.Srinath Parvathaneni2-311/+535
This patch adds support for SME ZA-targeting non-widening BFloat16 instructions, under tick FEAT_SME_B16B16 and command line flag "+sme-b16b16". FEAT_SME_B16B16 implements FEAT_SME2 and FEAT_SVE_B16B16, in accordance with that "+sme-b16b16" enables "+sme2" and "+sve-b16b16". Also the test files related to FEAT_SME_B16B16 are prefixed with sme-b16b16*. eg: sme-b16b16-1.s, sme-b16b16-1.d. The spec for this feature and instructions is availabe here [1]: [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 min and max instructions.Srinath Parvathaneni2-218/+283
This patch adds support for SME Z-targeting multi-vector non-widening BFloat16 instructions, under tick FEAT_SVE_B16B16 and command line flag "+sve-b16b16+sme2". Also the test files related to FEAT_SVE_B16B16 (+sme2) are prefixed with sve-b16b16-sme2*. eg: sve-b16b16-sme2-1.s, sve-b16b16-sme2-1.d. The spec for this feature and instructions is availabe here [1]: [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 feature.Srinath Parvathaneni1-14/+14
In the current code, SVE2 Bfloat16 instructions are implemented with tick FEAT_B16B16 and command line flag "+b16b16" and this feature was suspended due to incomplete support. In the new spec available here[1], FEAT_B16B16 is replaced with FEAT_SVE_B16B16 and command line flag "+b16b16" is replace with "sve-b16b16". Also the test files related to FEAT_SVE_B16B16 are prefixed with sve-b16b16*. eg: sve-b16b16-sve2-1.s, sve-b16b16-sve2-1.d. This patch supports the SVE Z-targeting non-widening BFloat16 instructions with command line flag "+sve-b16b16+sve2". [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SVE-Instructions?lang=en
2025-01-10aarch64: Make VGx4 symbol mandatory for fvdotb and fvdottAndrew Carlotti1-2/+2
Add tests for this, and update the existing fvdotb and fvdott tests to include the VGx4 symbol so that they continue to test for the intended errors.
2025-01-10aarch64: Rename AARCH64_OPND_SME_ZT0_INDEX2_12Andrew Carlotti3-5/+5
Rename to AARCH64_OPND_SME_ZT0_INDEX_MUL_VL.
2025-01-10aarch64: Remove redundant sme-lutv2 qualifiers and operandsAndrew Carlotti6-96/+70
2025-01-10aarch64: Fix incorrect gating of sme-lutv2 instructionsAndrew Carlotti1-4/+10
Only the strided form of the luti4 intrinsic requires FEAT_SME2p1.
2025-01-10aarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions.Srinath Parvathaneni2-218/+246
This patch adds support for FEAT_SME_F16F16 instructions fcvt and fcvtl, which are available on passing command line flags +sme-f16f16 and the spec is available here[1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.Srinath Parvathaneni2-286/+430
This patch adds support for FEAT_SME_F16F16 instructions fmla and fmls, which are available on passing command line flags +sme-f16f16 and the spec is available here[1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions.Srinath Parvathaneni2-185/+221
This patch adds support for FEAT_SME_F16F16 instructions fmops and fmopa, which are available on passing command line flags +sme-f16f16 and the spec is available here[1]. [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10x86: Support x86 Zhaoxin PadLockRNG2 instructionMayShao-oc7-4432/+4483
This patch adds support for Zhaoxin PadLock RNG2 instruction, the CPUID EDX bit[23] indicates its enablement, it includes REP XRNG2 instruction. gas/ChangeLog: * NEWS: Support Zhaoxin PadLock RNG2 instruction. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLock RNG2 instruction. (output_insn): Handle PadLock RNG2 instruction. * doc/c-i386.texi: Document PadLock RNG2. * testsuite/gas/i386/i386.exp: Add PadLock RNG2 test. * testsuite/gas/i386/padlock_rng2.d: Ditto. * testsuite/gas/i386/padlock_rng2.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockRNG2. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockRNG2): New. * i386-opc.tbl: Add Zhaoxin PadLock RNG2 instruction. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-09RISC-V: Fix display of partial instructionsCharlie Jenkins1-4/+49
As of commit e43d8768d909 ("RISC-V: Fix disassemble fetch fail return value.") partial instructions are no longer displayed by objdump. While that commit fixed the behavior of print_insn_riscv() returning the arbitrary status value upon failure, it caused the behavior of dumping instructions to change. Allow partial instructions to be displayed once again and only return -1 if no part of the instruction was able to be displayed. Fixes: e43d8768d909 ("RISC-V: Fix disassemble fetch fail return value.") Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Acked-By: Andrew Burgess <aburgess@redhat.com>
2025-01-08Support Intel AMX-FP8Liwei Xu7-1058/+1179
In this patch, we will support AMX-FP8 feature. Since in the foreseeable future, only AMX-MOVRS will also use VEX_MAP5, we currently will not add a table of 256 entries and handle just like MAP7. gas/ChangeLog: * config/tc-i386.c: Add amx_fp8. * doc/c-i386.texi: Document .amx_fp8. * testsuite/gas/i386/x86-64.exp: Run AMX-FP8 tests. * testsuite/gas/i386/x86-64-amx-fp8-bad.d: New test. * testsuite/gas/i386/x86-64-amx-fp8-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0): New. (X86_64_VEX_MAP5_FD): Ditto. (VEX_LEN_MAP5_FD_X86_64): Ditto. (VEX_W_MAP5_FD_X86_64_L_0):Ditto. (prefix_table): Add PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0. (x86_64_table): Add X86_64_VEX_MAP5_FD. (vex_len_table): Add VEX_LEN_MAP5_FD_X86_64. (vex_w_table): Add VEX_W_MAP5_FD_X86_64_L_0. * i386-gen.c: Add CPU_AMX_FP8_FLAGS and CPU_ANY_AMX_FP8_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: Add cpuamx_fp8. * i386-opc.tbl: Add AMX_FP8 instructions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2025-01-06x86/APX: simplify ENQCMD[,S} opcode table entriesJan Beulich2-8/+8
APX_F() makes sense to use only for dual VEX/EVEX templates; ENQCMD{,S} are legacy encoded though in their original forms. Make the entries match the MOVDIR{I,64B} sibling ones.
2025-01-02Support Intel AMX-TF32Haochen Jiang7-1090/+1172
In this patch, we will support AMX-TF32. It is a simple ISA comparing to the previous ones, so there is no special handling. gas/ChangeLog: * config/tc-i386.c: Add amx_tf32. * doc/c-i386.texi: Document .amx_tf32. * testsuite/gas/i386/x86-64.exp: Run AMX-TF32 tests. * testsuite/gas/i386/x86-64-amx-tf32-bad.d: New test. * testsuite/gas/i386/x86-64-amx-tf32-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F3848_X86_64_W_0_L_0): New. (X86_64_VEX_0F3848): Ditto. (VEX_LEN_0F3848_X86_64_W_0): Ditto. (VEX_W_0F3848_X86_64): Ditto. (prefix_table): Add PREFIX_VEX_0F3848_X86_64_W_0_L_0. (x86_64_table): Add X86_64_VEX_0F3848. (vex_len_table): Add VEX_LEN_0F3848_X86_64_W_0. (vex_w_table): Add VEX_W_0F3848_X86_64. * i386-gen.c (isa_dependencies): Add AMX_TF32. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_TF32): New. (i386_cpu_flags): Add cpuamx_tf32. * i386-opc.tbl: Add AMX-TF32 instructions. * i386-tbl.h: Regenerated.
2025-01-02Support Intel AMX-TRANSPOSEHaochen Jiang8-11454/+11755
In this patch, we will support AMX-TRANSPOSE. Since AMX-TRANSPOSE will be used with other CPUIDs very often, we put it into CPU_FLAGS_COMMON. To implement TMM pair, we reused ImplicitGroup and adjust the condition in process_operands for the instructions. APX_F extension is also handled in this patch, where it extends T2RPNTLVW[Z0,Z1][,T1] to EVEX.128.NP/66.0F38.W0 6E/6F !(11):rrr:100 with NF=0. Also, TTDPFP16PS should base on AMX_FP16, not AMX_BF16 in ISE055. It would be fixed in ISE056. gas/ChangeLog: * config/tc-i386.c (cpu_arch): Add amx_transpose. (_is_cpu): Ditto. (process_operands): Adjust the condition for AMX-TRANSPOSE. * doc/c-i386.texi: Document .amx_transpose. * testsuite/gas/i386/x86-64.exp: Run AMX-TRANSPOSE tests. * testsuite/gas/i386/x86-64-amx-transpose-bad.d: New test. * testsuite/gas/i386/x86-64-amx-transpose-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.s: Ditto. opcodes/ChangeLog: * i386-dis.c (MOD_VEX_0F386E_X86_64_W_0): New. (MOD_VEX_0F386F_X86_64_W_0): Ditto. (PREFIX_VEX_0F385F_X86_64_W_0_L_0): Ditto. (PREFIX_VEX_0F386B_X86_64_W_0_L_0): Ditto. (PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0): Ditto. (PREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0): Ditto. (X86_64_VEX_0F385F): Ditto. (X86_64_VEX_0F386B): Ditto. (X86_64_VEX_0F386E): Ditto. (X86_64_VEX_0F386F): Ditto. (VEX_LEN_0F385F_X86_64_W_0): Ditto. (VEX_LEN_0F386B_X86_64_W_0): Ditto. (VEX_LEN_0F386E_X86_64_W_0_M_0): Ditto. (VEX_LEN_0F386F_X86_64_W_0_M_0): Ditto. (VEX_W_0F385F_X86_64): Ditto. (VEX_W_0F386B_X86_64): Ditto. (VEX_W_0F386E_X86_64): Ditto. (VEX_W_0F386F_X86_64): Ditto. (mod_table): Add MOD_VEX_0F386E_X86_64_W_0, MOD_VEX_0F386F_X86_64_W_0. (prefix_table): Add PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0, PREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0. Add new instructions for PREFIX_VEX_0F386C_X86_64_W_0_L_0. (x86_64_table): Add X86_64_VEX_0F385F, X86_64_VEX_0F386B, X86_64_VEX_0F386E, X86_64_VEX_0F386F. (vex_len_table): Add VEX_LEN_0F385F_X86_64_W_0, VEX_LEN_0F386B_X86_64_W_0, VEX_LEN_0F386E_X86_64_W_0_M_0, VEX_LEN_0F386F_X86_64_W_0_M_0. (vex_w_table): Add VEX_W_0F385F_X86_64, VEX_W_0F386B_X86_64, VEX_W_0F386E_X86_64, VEX_W_0F386F_X86_64. * i386-gen.c (cpu_flag_init): Add AMX_TRANSPOSE. (cpu_flags): Add CpuAMX_TRANSPOSE. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_TRANSPOSE): New. (i386_cpu): Add cpuamx_transpose. * i386-opc.tbl: Add AMX-TRANSPOSE instructions. * i386-tbl.h: Regenerated. Co-authored-by: Hu, Lin1 <lin1.hu@intel.com>
2025-01-01Update year range in copyright notice of binutils filesAlan Modra272-276/+276
2024-12-24arc: add_to_decodelistAlan Modra1-147/+124
Given objdump -Mcpu=archs -D or similar, add_to_decodelist adds three entries to decodelist for each instruction disassembled. That can waste a lot of cpu when the list grows large. What's more, decodelist is static and nothing clears the list. So the list persists from one file to the next if objdump is disassembling multiple files in one invocation. Wrong disassembly might result. To fix this problem, I've moved decodelist to the arc private_data and made it an array. I believe that init_disassemble_data will be called, clearing private_data, for each file disassembled. That's certainly true for objdump, and if I can see my way around gdb constructors, it's also true for gdb. I don't think there is a possibility of info.disassembler_options changing unless there is first a call to init_disassebled_data. That means all of the option parsing and bfd mach and e_flags decoding need only be done when initialising the arc private_data. * arc-dis.c (addrtypenames_max, addrtypeunknown): Delete.. (get_addrtype): ..substitute values here. Tidy. (skipclass_t, linkclass, decodelist): Delete. (enforced_isa_mask, print_hex): Delete. (struct arc_disassemble_info): Add decode[], decode_count, isa_mask, print_hex. (init_arc_disasm_info): Tidy. (add_to_decodelist): Delete, replacing with.. (add_to_decode): ..this. Don't duplicate entries. (skip_this_opcode): Adjust to suit. (find_format_from_table, parse_option): Likewise. (parse_disassembler_options): Likewise. Move code dealing with bfd mach and eflags from.. (print_insn_arc): ..here. Adjust for other changes.
2024-12-23Support Intel AVX10.2 minmax, vector copy and compare instructionsHaochen Jiang8-2255/+2562
In this patch, we will support AVX10.2 minmax, vector copy and compare instructions. This will finish the new instruction form support for AVX10.2. Most of them are new instructions forms except for vmovd and vmovw, which are extended usage from the old ones. gas/ChangeLog: * NEWS: Mention AVX10.2. * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-5-intel.d: New test. * testsuite/gas/i386/avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/avx10_2-512-miscs-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-miscs.d: Ditto. * testsuite/gas/i386/avx10_2-512-miscs.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-miscs-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-miscs.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-miscs.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-len.h: Add EVEX_LEN_0F7E_P_1_W_1, EVEX_LEN_0FD6_P_2_W_0, EVEX_LEN_MAP5_6E and EVEX_LEN_MAP5_7E. * i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F3A52, PREFIX_EVEX_0F3A53, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_6E and PREFIX_EVEX_MAP5_7E. * i386-dis-evex-w.h: Adjust EVEX_W_0F3A42, EVEX_W_0F7E_P_1 and EVEX_W_0FD6. Add EVEX_W_MAP5_6E_P_1 and EVEX_W_MAP5_7E_P_1. * i386-dis-evex.h: Add and adjust table entries for AVX10.2. * i386-dis.c (PREFIX_EVEX_0F2E): New. (PREFIX_EVEX_0F2F): Ditto. (PREFIX_EVEX_0F3A52): Ditto. (PREFIX_EVEX_0F3A53): Ditto. (PREFIX_EVEX_MAP5_2E): Ditto. (PREFIX_EVEX_MAP5_2F): Ditto. (PREFIX_EVEX_MAP5_6E_L_0): Ditto. (PREFIX_EVEX_MAP5_7E_L_0): Ditto. (EVEX_LEN_0F7E_P_1_W_1): Ditto. (EVEX_LEN_0FD6_P_2_W_0): Ditto. (EVEX_LEN_MAP5_6E): Ditto. (EVEX_LEN_MAP5_7E): Ditto. (EVEX_W_MAP5_6E_P_1): Ditto. (EVEX_W_MAP5_7E_P_1): Ditto. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Jun Zhang <jun.zhang@intel.com> Co-authored-by: Zewei Mo <zewei.mo@intel.com>
2024-12-18Support Intel SM4 AVX10.2 extensionHaochen Jiang6-9281/+9309
In this patch, we will support SM4 AVX10.2 extension part. It is a promotion from VEX encoding to EVEX encoding. The EVEX encoding is based on AVX10.2, which is the same as the upcoming MOVRS ISA. Thus, we decide to pull AVX10.2 out to CPU_COMMON_FLAGS. While I have also tried to merge the table like AVX/AVX512, I choose to just templatize the table. I am okay to go either way, but slightly prefer the templatizing one since probably SM4 would be the only ISA with AVX10.2 needs such VEX to EVEX extension (MOVRS does not need that). Also, it is a tendancy that we will directly provide EVEX encodings and no VEX encodings for vector instructions since AVX10. This will make the adding in gas/config/tc-i386.c not that worthy. gas/ChangeLog: * NEWS: Support Intel SM4 EVEX instructions. * config/tc-i386.c (_is_cpu): Handle AVX10.2. * testsuite/gas/i386/i386.exp: Run SM4 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-sm4-intel.d: Add SM4 tests. * testsuite/gas/i386/avx10_2-256-sm4.d: Ditto. * testsuite/gas/i386/avx10_2-256-sm4.s: Ditto. * testsuite/gas/i386/avx10_2-512-sm4-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-sm4.d: Ditto. * testsuite/gas/i386/avx10_2-512-sm4.s: Ditto. * testsuite/gas/i386/avx10_2-sm4-inval.l: Ditto. * testsuite/gas/i386/avx10_2-sm4-inval.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-sm4-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-sm4.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-sm4.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-sm4-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-sm4.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-sm4.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-sm4-inval.l: Ditto. * testsuite/gas/i386/x86-64-avx10_2-sm4-inval.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add evex table entry for SM4. * i386-dis.h: Ditto. * i386-opc.h: (i386_cpu): Move AVX10.2 to CPU_FLAGS_COMMON. * i386-opc.tbl: Add SM4 EVEX instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2024-12-16Update translations for the opcodes directory for the French and Serbian ↵Nick Clifton2-976/+861
languages.
2024-12-09PowerPC: Disallow r0 as a base register for the hashst and hashchk insnsPeter Bergner1-7/+7
Using r0 as a base address register in the ROP hashst and hashchk instructions is invalid. Modify the assembler to catch that illegal use and emit an error. opcodes/ * ppc-opc.c (insert_ras): Update error message and function comment. (powerpc_opcodes) <hashst, hashstp, hashchk, hashchkp>: Use RAS.
2024-12-09LoongArch: Assign DWARF register numbers to register aliasesLulu Cai1-0/+32
.cfi directives only support the use of register numbers and not register names or aliases. This commit adds support for 4 formats, for example: .cfi_offset r1, 8 .cfi_offset ra, 8 .cfi_offset $r1,8 .cfi_offset $ra,8 The above .cfi directives are equivalent and all represent dwarf register number 1. Display register aliases as specified in the psABI during disassembly.
2024-12-05Support Intel AVX10.2 satcvt instructionsHu, Lin17-658/+1176
In this patch, we will support AVX10.2 satcvt instructions. All of them are new instruction forms. In current documentation, it is still VCVTTNEBF162I[,U]BS, but it will change to VCVTTBF162I[,U]BS eventually. In table part, we used temporary <sign> iterator to reduce redundancy. It definitely could be done for legacy cvt insns, but it is out of this patch's scope. gas/ChangeLog: * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-512-satcvt-intel.d: New test. * testsuite/gas/i386/avx10_2-512-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-512-satcvt.s: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP5_68, PREFIX_EVEX_MAP5_69, PREFIX_EVEX_MAP5_6A, PREFIX_EVEX_MAP5_6B, PREFIX_EVEX_MAP5_6C, PREFIX_EVEX_MAP5_6D. * i386-dis-evex-w.h: Add EVEX_W_MAP5_6C_P_0, EVEX_W_MAP5_6C_P_2, EVEX_W_MAP5_6D_P_0, EVEX_W_MAP5_6D_P_2. * i386-dis-evex.h (prefix_table): Add PREFIX_EVEX_MAP5_68, * PREFIX_EVEX_MAP5_69, PREFIX_EVEX_MAP5_6A, PREFIX_EVEX_MAP5_6B. * i386-dis.c: (PREFIX_EVEX_MAP5_68): New. (PREFIX_EVEX_MAP5_69): Ditto. (PREFIX_EVEX_MAP5_6A): Ditto. (PREFIX_EVEX_MAP5_6B): Ditto. (PREFIX_EVEX_MAP5_6C): Ditto. (PREFIX_EVEX_MAP5_6D): Ditto. (EVEX_MAP5_6C_P_0): Ditto. (EVEX_MAP5_6C_P_2): Ditto. (EVEX_MAP5_6D_P_0): Ditto. (EVEX_MAP5_6D_P_2): Ditto. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Zewei Mo <zewei.mo@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> Co-authored-by: Levy Hsu <admin@levyhsu.com>
2024-12-05x86: Eliminate unnecessary {evex} prefixesH.J. Lu4-11/+29
For several instructions including vps{l,r}l{d,q,w,dq} and vpsra{d,w}, their VEX part do not have the following version: vpsrlw $0x1f,(%r15,%rcx,4),%xmm0 Thus, {evex} prefix should not be inserted when their second operand is memory, while we still need them for register as second operand. Add a new macro %ME to solve this problem. For vpsraq, there is no VEX version, so the {evex} prefix should always be eliminated. gas/ChangeLog: PR binutils/32403 * testsuite/gas/i386/i386.exp: Run new test. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/evex-only.d: New test. * testsuite/gas/i386/evex-only.s: Ditto. * testsuite/gas/i386/x86-64-evex-only.d: Ditto. * testsuite/gas/i386/x86-64-evex-only.s: Ditto. opcodes/ChangeLog: PR binutils/32403 * i386-dis-evex-reg.h: Use %ME instead of %XE for vps{l,r}l{w,dq} and vpsraw. Split table for vpsra{d,q}. * i386-dis-evex-w.h: Use %ME instead of %XE for vps{l,r}l{d,q} and vpsrad. Eliminate vpsraq {evex} prefix. * i386-dis-evex.h: Split table for vpsra{d,q}. * i386-dis.c: (EVEX_W_0F72_R_4): New. (EVEX_W_0FE2): Ditto. (struct dis386): Add comment for %ME. (putop): Handle %ME. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-12-03PowerPC: Add support for RFC02680 - PQC Acceleration InstructionsSurya Kumari Jangala1-0/+10
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvadduwm, xvadduhm, xvsubuwm, xvsubuhm, xvmuluwm, xvmuluhm, xvmulhsw, xvmulhsh, xvmulhuw, xvmulhuh. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
generated by cgit v1.1 at 2025-09-20 21:42:42 +0000